HMC778 How to mute output signal and force LD low?

HMC778 after powerup (without registers programming) working on maximum VCO Output Frequency (about 10.9 GHz) and LD is unstable: sometimes LD=1 or LD=0, or fastly switching between 1 and 0.

How to disable output and force LD=0 (in other words: how to disable VCO and PLL)?

I tried writing 0x000000 to Reg 0x01 - no way
also tried writing 0x000000 to Reg 0x08 - no effect

i work in HMC mode SPI and CE pin is permanently high (can't control)

Parents
  • +1
    •  Analog Employees 
    on Jul 26, 2019 7:44 PM over 1 year ago in reply to Feruz

    Hi, 

    Disabling the VCO and PLL are not the same as forcing the LD value to equal zero since anytime the synthesizer is not phase locked, the LD bit will equal zero. 

    The PLL can be disabled by setting REG 0x01[1:0] = 0  (verified using evaluation board and software). As long as pin 31 (DVDD) retains 3.3V (or remains above the threshold voltage) the register contents will be preserved. Note that the VCO will remain powered up but you will notice a 50 mA reduction in current indicating that the PLL is powered down. 

    The VCO can only be disabled or muted by powering down the supply on VCCVCO1 (pin 40). This could easily be controlled via one of our switches and might be required in applications where current consumption is a concern. If using the HMC976LP3E regulator you could use the switch to open the path to the EN pin.

    If you simply desire to mute the output of the HMC778LP6GE then I recommend you add one of our low insertion loss, non-reflective switches such as the HMC1118 in the output path. 

    The LD function can be disabled in REG 0x0F (actually disables output from SDO pin), LD can be read from REG 0x12[1]. If you simply want to force LD to equal 0 you could tri-state the charge pump outputs by disabling them, simply set REG 0x0B[6:5] = 0. Setting charge pump up / down gain to equal 0mA in REG 09[13:0] = 0 would achieve a similar result. 

    Hope this helps, 

    Marty 

Reply
  • +1
    •  Analog Employees 
    on Jul 26, 2019 7:44 PM over 1 year ago in reply to Feruz

    Hi, 

    Disabling the VCO and PLL are not the same as forcing the LD value to equal zero since anytime the synthesizer is not phase locked, the LD bit will equal zero. 

    The PLL can be disabled by setting REG 0x01[1:0] = 0  (verified using evaluation board and software). As long as pin 31 (DVDD) retains 3.3V (or remains above the threshold voltage) the register contents will be preserved. Note that the VCO will remain powered up but you will notice a 50 mA reduction in current indicating that the PLL is powered down. 

    The VCO can only be disabled or muted by powering down the supply on VCCVCO1 (pin 40). This could easily be controlled via one of our switches and might be required in applications where current consumption is a concern. If using the HMC976LP3E regulator you could use the switch to open the path to the EN pin.

    If you simply desire to mute the output of the HMC778LP6GE then I recommend you add one of our low insertion loss, non-reflective switches such as the HMC1118 in the output path. 

    The LD function can be disabled in REG 0x0F (actually disables output from SDO pin), LD can be read from REG 0x12[1]. If you simply want to force LD to equal 0 you could tri-state the charge pump outputs by disabling them, simply set REG 0x0B[6:5] = 0. Setting charge pump up / down gain to equal 0mA in REG 09[13:0] = 0 would achieve a similar result. 

    Hope this helps, 

    Marty 

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