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ADRF6720-27 EVALZ

I was working with the evaluation board, and things seem to be working correctly.

The board seemed to deteriorate from "locked" but with a frequency 5MHZ off from the desired frequency.  Now I am not seeing any lock at all.

Is there some insight about what could be causing it not to lock?  I have a precision clock feed to the SMA connector, and I have checked power and SPI registers and nothing looks wrong.  Is it possible that the board was damaged by my probing?  

I have populated this device on our prototype and I am able to see a lock on the our prototype board.  However, I am only able to achieve lock by holding the ENBL on all the time.  This is not feasible for our final design.  I believe on the eval board (before it stopped working) after it locked initially I could turn it on/off via the switch.  I can provide any additional information if needed via email.

Thanks.



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[edited by: lallison at 5:04 PM (GMT 0) on 16 Jul 2019]
  • Not sure the cause of the loss of functionality, but I replaced the part and the board is working again.  Not sure if there was a spike on the supply voltage that caused this part to go south.

    As far as the prototype I am able to see an output on the IQ modulator now.  I have the following values set on address 0x01 & 0x10: 0x063E.  On the evaluation board I only see a 100mA drop in current when I disable the ENBL pin.  I did see a post on the forum that shows writing 0x0601 to address 0x10 which will not disable the PLL.  However, I still see a significant amount of current draw (transmitting vs disabled).  Is there some more insight to how the ENBL can be used to conserve more power?

  • Hello,

    Sorry for late.

    If it is 5MHz offset from the desired frequency, it is not locked. If you zoom in it by narrowing span, the signal may move around. If it is the case,

    We need to check;

    • if Reference / PFD Frequency are in the frequency range and in the amplitude specified in spec table 1(section Reference Characteristics).
    • if we configure part correctly including Enable settings, the right VCO selection among four VCO(refer to Table6), and Table9.
    • Vtune voltage (it would be around 1.7V @ 25C)  and check/replace a loop filter.

    ENBL : This is to control the RF output quickly (disable or enable). You don't need to hold the ENBL high on all the time. If you set the bit at reg 0x10 "0", the block is only controlled by reg.0x01 through SPI. When it is "1" on both reg.0x01 and reg.0x10, then this block is controlled by the logic level on ENBL pin.  I believe LO related block(PLL,VCO) shouldn't be disabled/enabled by ENBL since it takes specific process and sequences.

    Thanks

    Tony

  • Hello,

    Good to hear it works now by replacing a part. Not sure if the part was damaged or not and how it happened.

    If you set reg.0x01 and reg.0x10 same at 0x063E, then most blocks will be disabled by ENBL logic low but as I commented early, it is suggested to keep LO enabled(not disabled by ENBL) by setting reg.0x10 0x0601 for example. That means we can still save current by ENBL but less current saving. We can save current by setting LD_DRV_LVL(Reg.0x22[7:6] through SPI. 

    Unfortunately, I don't have data how much current is controlled by an individual bit on reg.0x01 but anyway, there is limitation at current saving by ENBL. 

    Thanks

    Tony

  • Thank you for your support.

    My application has a very infrequent transmit requirement (several milliseconds between transmissions).  Therefore we can afford the PLL to calibrate again before the next transmit.  If that is the case, is there still an issue with disabling the LO related blocks?  We would really like to conserve our power consumption, because the power supply is supplied on another board and cannot sustain continuous current draw.

    The value I have currently written to 0x22 is 0x3A0A.  Bits 7:6 are both zero which is the lowest value on the LO_DRV_LVL.  So does that mean I have to sequence the ADRF6720-27 everytime before I transmit?  Basically writing the INT, FRAC, DIV registers to re-enable calibration of the LO?

    My current register settings are:

    0x01: 0x063E

    0x02: 0x0027

    0x03: 0x0078

    0x04: 0x03E8

    0x10: 0x063E

    0x20: 0x0C26

    0x21: 0x0008

    0x22: 0x3A0A

    0x30: 0x000A

    0x31: 0x1101

    0x32: 0x0900

    0x33: 0x0000

    0x40: 0x0010

    0x42: 0x000E

    0x43: 0x0000

    0x44: 0x0000

    0x49: 0x14B4