HMC807 phase Noise

Hi,

From HMC807 datasheet page 4. It show loop BW=100K & Reference=50MHz is better than BW=10K & Reference=10MHz .

My question: Is the loop BW=100K is good design or Reference =50MHz is good? I think the reference frequency should not effect the phase?Am I right?

It may the reference 10MHz phase noise worse than 100Mhz,Am I right?

Parents
  • +1
    •  Analog Employees 
    on May 29, 2019 2:31 PM

    Hello, 

    This is a length answer but covers the basics at a high level.  

    First I recommend you review the HMC703 and HMC704 plots for FOM performance as well as the FOM, Noise Floor and Flicker noise section. Unlike the PLL used in the HMC807, these models include an additional internal prescaler  prior to the N counter but the information is still relevant as most PLL's will respond in a similar manner. 

    With respect to the closed loop phase noise performance there are a lot of factors to consider; most of these impact the performance across certain offset ranges.

    Some of these include:

    1) Reference quality (typically impacts noise <1 kHz but could extend further if reference has high phase noise) impacted by:

    a) Phase noise

    b) Slew rate 

    c) drive level

    2) PLL FOM (primarily affects in-band noise, 1 kHz to loop filter corner) which for a given PLL is impacted by:

    a) N counter value for desired phase locked frequency - N counter value which is derived using the operating frequency and the  Phase  Frequency Detector frequency (PFD) which is derived using Reference freq / R Divider value. 

    b) Mode (FRAC vs Int)

    c) SDM order / mode if operating in frac mode

    d) charge pump current

    e) charge pump voltage (particularly it's value relative to charge pump rail).

    f) loop design

    a) loop bandwidth (in-band noise degrades as BW is reduced following slope of the VCO phase noise) 

    b) phase margin (reduced phase margin is likely the cause of the peaking in the 10 kHz example above). 

    c) capacitor type (NPO / COG best, never use worse than X7R)

    d) active loops - op amp noise, bias current and gain BW product impact loop performance

    3) VCO Phase Noise (impacts noise at offsets beyond loop filter corner)

    4) additional multipliers, dividers, amplifier added at RFOUT will degrade noise linearly as a function of their residual phase noise. Typically at offsets from 1 MHz and higher.

    If the loop BW for the plot in the HMC807 was kept the same and only the PFD frequency reduced we would expect to see a 10* LOG (5) = 7 dBc / Hz degradation in-band. Since we are still at 12.9 GHz and the loop BW was also changed and at a 10 kHz  LBW we remain  beyond the flicker corner for the VCO, we must also add in 20 * LOG (50 MHz / 10 MHz) = 14 dBc / Hz for a total increase of 21 dBc / Hz at offsets inside the loop. band.

    Depending on the loop order / design, the VCO noise at offsets beyond the loop are impacted out to an offset that is roughly 20 * loop BW. Beyond this we should measure the open loop VCO noise performance. The loops look like they are actually wider than published but you can see that this assumption holds in the plot above.  

    Best regards, 

    Marty

Reply
  • +1
    •  Analog Employees 
    on May 29, 2019 2:31 PM

    Hello, 

    This is a length answer but covers the basics at a high level.  

    First I recommend you review the HMC703 and HMC704 plots for FOM performance as well as the FOM, Noise Floor and Flicker noise section. Unlike the PLL used in the HMC807, these models include an additional internal prescaler  prior to the N counter but the information is still relevant as most PLL's will respond in a similar manner. 

    With respect to the closed loop phase noise performance there are a lot of factors to consider; most of these impact the performance across certain offset ranges.

    Some of these include:

    1) Reference quality (typically impacts noise <1 kHz but could extend further if reference has high phase noise) impacted by:

    a) Phase noise

    b) Slew rate 

    c) drive level

    2) PLL FOM (primarily affects in-band noise, 1 kHz to loop filter corner) which for a given PLL is impacted by:

    a) N counter value for desired phase locked frequency - N counter value which is derived using the operating frequency and the  Phase  Frequency Detector frequency (PFD) which is derived using Reference freq / R Divider value. 

    b) Mode (FRAC vs Int)

    c) SDM order / mode if operating in frac mode

    d) charge pump current

    e) charge pump voltage (particularly it's value relative to charge pump rail).

    f) loop design

    a) loop bandwidth (in-band noise degrades as BW is reduced following slope of the VCO phase noise) 

    b) phase margin (reduced phase margin is likely the cause of the peaking in the 10 kHz example above). 

    c) capacitor type (NPO / COG best, never use worse than X7R)

    d) active loops - op amp noise, bias current and gain BW product impact loop performance

    3) VCO Phase Noise (impacts noise at offsets beyond loop filter corner)

    4) additional multipliers, dividers, amplifier added at RFOUT will degrade noise linearly as a function of their residual phase noise. Typically at offsets from 1 MHz and higher.

    If the loop BW for the plot in the HMC807 was kept the same and only the PFD frequency reduced we would expect to see a 10* LOG (5) = 7 dBc / Hz degradation in-band. Since we are still at 12.9 GHz and the loop BW was also changed and at a 10 kHz  LBW we remain  beyond the flicker corner for the VCO, we must also add in 20 * LOG (50 MHz / 10 MHz) = 14 dBc / Hz for a total increase of 21 dBc / Hz at offsets inside the loop. band.

    Depending on the loop order / design, the VCO noise at offsets beyond the loop are impacted out to an offset that is roughly 20 * loop BW. Beyond this we should measure the open loop VCO noise performance. The loops look like they are actually wider than published but you can see that this assumption holds in the plot above.  

    Best regards, 

    Marty

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