Phase detector of the HMC807LP6CE does not work - 3

Hi Dmitry, 

I went back to your earlier messages and modeled your loop using ADISimPLL v 5.00.03 (op amps were removed accidentally in the latest version apparently so this is an earlier version of ADISimPLL). I used the AD4625 op amp as this is a good choice for an op amp a as it doesn't degrade the noise performance much vs the ideal op amp and phase locks to 10 Hz per the simulation. If during synthesis, ADISimPLL doesn't indicate that the loop will lock it usually will not work when you try to realize it on the bench. I highly recommend that ADISimPLL be used to verify loop filter design and op amp selection prior to fabrication to eliminate a lot of frustration. No offense but I found your schematic confusing, particularly the SPI portion / LD.  Definitely could be problems here. 

ADISimPLL indicates that for 12800 MHz and a PFD frequency of 10 MHz that this loop is degrading the far out VCO noise by abut 10dBc/Hz and it will not lock. You mention above that R = 1 but your file shows 0x02000002 which would indicate PLL register 2 = 2 or a PFD frequency of 5 MHz. Please clarify). Neither PFD frequency allows lock. 

For improved phase noise and spurious performance and values that allow lock use the following ADISimPLL values (REF designators are from ADISimPLL). Loop preserves a 29.2 kHz loop BW and 58 degrees of PM with a 10 MHz PFD freq

R1 = 620 ohms

C1 = 270pF

R2 = 680 ohms

C2 = 68nF

C3 = 750 pF

R3 = 1.5k ohms

C4 = 390pF 

Register file info is missing a lot registers. Please provide a complete register file - all registers listed in the user guide for the HMC807 please. 

Best Regards, 

Marty