Operation and Usage of ADPA7001CHIPS

As per the Simplified Block Diagram is given in the datasheet, It looks like Section A(main Amp) and Section B(Alternative Amp) pins are shorted.

So it is possible to use this component as:

  • Supplying 3.5V at VDD1A, VDD2A, VDD3A, and VDD4A.
  • And Setting the IDD current to 350mA using VGG12B and VGG34B.
  • Making sure VDD1B, VDD2B, VDD3B, VDD4B, VGG12A, and VGG34A are not connected.

Although as per the naming convention it does not feels right but I want to know are these Pins internally shorted or not.

Thanks in Advance! 

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  • Hello harshs1,

    I am the engineer who drew the diagram shown on the ADPA7001CHIPS data sheet. I did so after reviewing the die layout.

    The VDD1A and VDD1B pads are indeed connected to each other by on-chip metal (no resistors). Likewise with VDD2A and VDD2B. Likewise with VDD3A and VDD3B. Likewise with VDD4A and VDD4B. The VDD1 pads do not connect to the VDD2, VDD3, and VDD4 pads. Basically, the A and B pads of a given numbered VDD (e.g. VDD1) connect to each other, but not to any VDD pads of a different number. That is what is shown in Figure 40: Four gain stages, each with its own drain pads.

    The VGG12 pads are for gate bias of gain stages 1 & 2. The VGG34 pads are for gate bias of gain stages 3 & 4. The VGG12 pads do not make connection to the VGG34 pads. There is some intentional resistance between the VGG12A and VGG12B pads. There is also some intentional resistance between the VGG34A and VGG34B pads.

    Though we don't show this on the data sheet, it is indeed possible to apply drain bias to the A pads (in the North) and apply gate bias to the B pads (in the South)...though we did not evaluate the part in that manner since we had limited time and die available. It is also possible to apply drain bias to the B pads (in the South) and apply gate bias to the A pads (in the North)...though again, we did not evaluate the part in that manner.

    Let me know if you have additional questions.

    Regards,

    SMcBride

Reply
  • Hello harshs1,

    I am the engineer who drew the diagram shown on the ADPA7001CHIPS data sheet. I did so after reviewing the die layout.

    The VDD1A and VDD1B pads are indeed connected to each other by on-chip metal (no resistors). Likewise with VDD2A and VDD2B. Likewise with VDD3A and VDD3B. Likewise with VDD4A and VDD4B. The VDD1 pads do not connect to the VDD2, VDD3, and VDD4 pads. Basically, the A and B pads of a given numbered VDD (e.g. VDD1) connect to each other, but not to any VDD pads of a different number. That is what is shown in Figure 40: Four gain stages, each with its own drain pads.

    The VGG12 pads are for gate bias of gain stages 1 & 2. The VGG34 pads are for gate bias of gain stages 3 & 4. The VGG12 pads do not make connection to the VGG34 pads. There is some intentional resistance between the VGG12A and VGG12B pads. There is also some intentional resistance between the VGG34A and VGG34B pads.

    Though we don't show this on the data sheet, it is indeed possible to apply drain bias to the A pads (in the North) and apply gate bias to the B pads (in the South)...though we did not evaluate the part in that manner since we had limited time and die available. It is also possible to apply drain bias to the B pads (in the South) and apply gate bias to the A pads (in the North)...though again, we did not evaluate the part in that manner.

    Let me know if you have additional questions.

    Regards,

    SMcBride

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