Lock time with HMC703 + HMC733

Hi AD experts,

I have an issue with the lock time of the PLL HMC703.

I made a direct measure with a mixer, a RF generator and observe the oscillation at DC with an oscilloscope. The RF generator and the PLL have the same reference. I measure a lock time of 120us at 10kHz instead of 30us with ADSIMPLL and 40us with the output pin LD_SDO of the PLL.

The configuration of the PLL is PLL HMC703 + VCO HMC733 + divider HMC862A. I measure the lock time from 12G to 19.8G.



  • +1
    •  Analog Employees 
    on Apr 25, 2019 3:14 PM

    The HMC733 has a bug in that the output buffer may generate a 7.5GHz sub-harmonic with Vtune around 8V (15G output).  When sweeping from 19.8GHz to 12GHz the HMC703 may try to lock on this sub-harmonic which causes the sweep to stop as Vtune enters the problem region.  There is no problem sweeping the other way from 12GHz to 19.8GHz since the sub-harmonic is below the desired stop frequency.  The PLL continues to sweep through the problem region and the PLL locks reliably at 19.8GHz.  

    This bug has been fixed in the ADF5709.  This new part is a pin compatible replacement for HMC733 scheduled for release later this year.

  • Hi,

    Thanks for your answer.

    I add a 50R hyper resistor in parrallel at the output of the VCO to avoid the disturbance at 15G. The PLL locks correctly from 12G to 20G. 

    I have nearly the same lock time from 12-19.8 as 19.8-12. The lock time is 120us instead of 30us with simulation and 40us with the measurment through the LD_SDO.

    19.8G to 12G

    19.8 to 12G


  • 0
    •  Analog Employees 
    on Apr 30, 2019 1:17 PM in reply to nicolas_22

    Hi Nicolas,

    I apologize for the delay, I was out of the office last week. Typically ADISimPLL is fairly accurate so I'm surprised your seeing such a large discrepancy. Would it be possible for you to share your schematic or at least the portion of the schematic around the synthesizer that involves the components you mention above? Also if you could share the register file for each frequency your hopping to as well as your ADISimPLL file that would be very helpful. 



  • 0
    •  Analog Employees 
    on Apr 30, 2019 1:57 PM in reply to nicolas_22

    It doesn't make sense why LD_SDO indicates lock after 40us since according to your mixer output the VCO frequency is still off by 8.3KHz at 120us.

    Regardless of the LD_SDO discrepancy, ADIsimPLL predicts 10KHz lock time closer to 30us instead of 120us.  Check all simulation parameters match your actual circuit.  Loop filter components, charge pump setting, VCO tuning law and op-amp output saturation voltages all affect transient response.

    It would be useful to look at your schematic and ADIsimPLL file.  You can pass this to me at dean.young@analog.com if you don't want to post this information.