ADAR1000 Eval board PA_BIAS not working


I have got the evaluation board for ADAR1000 and I was trying to generate PA_BIAS using the internal DAC, but not able to do so. I am interfacing the board with the software provided from you. I am following the below table from the datasheet:

I tried all the combinations described above in the GUI to generate some voltage on the pin 23 of connector P9A on the board which corresponds to PA_BIAS1. But I see nothing at all on the multimeter. 

On the GUI, these are the steps I followed in order:

1. Connect to the board using ADDR0/1 = 0 (jumpers are left open)

2. Initialized TX on the tab "Tx Control"

3. Wrote some values to off and on registers shown below and enabled BIAS_CTRL

4. Enabled TX_EN under T/R Control tab

5. Checked the multimeter on pin23 of connector P9A, to see nothing.

I also tried with LNA_BIAS_OUT feature but also seeing no output voltage. 

Am I missing something here?



  • 0
    •  Analog Employees 
    on Apr 8, 2019 7:37 PM over 1 year ago

    Are you still having trouble getting the PA and LNA bias pins to work properly?

  • Hi, sorry for delayed response. The current on 3.3V supply is 20mA and on the -5V supply its 10mA

    And yes, its still not working.

  • Hi,

    After getting the PA_BIAS to work on the eval board, I tried interfacing this eval board with our zynq fpga board. The SPI lines from our FPGA were connected to the SPI lines on P3 connector of the ADAR eval board. Then I did the following sequence of SPI writes:

    (Please note that the below log is from the ADAR eval software and the sequence is the same as explained above in the original question, to change the PA1_BIAS voltage. I used this log to actually perform the same sequence of reg writes using our FPGA.)

    00:27:09: 00018 written to part
    00:27:09: 02F47 written to part
    00:27:09: 03142 written to part
    00:27:09: 03406 written to part
    00:27:09: 0363E written to part
    00:27:09: 03B40 written to part
    00:27:09: 01C7F written to part
    00:27:09: 02036 written to part
    00:27:09: 02136 written to part
    00:27:09: 02802 written to part
    00:27:09: 02800 written to part
    00:27:17: 03140 written to part
    00:27:24: 03040 written to part
    00:27:32: 02950 written to part
    00:27:32: 02A00 written to part
    00:27:32: 02B00 written to part
    00:27:32: 02C00 written to part
    00:27:32: 02D00 written to part
    00:27:36: 00000 written to part
    00:27:45: 03860 written to part

    I have verified the SPI lines from FPGA using an oscilloscope and made sure that all the housekeeping rules explained in this post are adhered.

    I also checked the ADDR0/1 lines are set to 0, and the PA_ON GPIO is also set to 0.

    I expected to see the PA1_BIAS voltage change to 1.5V but I dont see any change in its value. DId I miss something? Can you please help?


  • 0
    •  Analog Employees 
    on Apr 17, 2019 10:20 PM over 1 year ago in reply to gensysco

    There must be some missing writes, as I think I found why PA1 Bias does not change.  I've gone through your writes and commented on what each does:


    00018:  Activate SDO
    02F47:  Enable Tx VGA, Tx Vector Modulator, Tx Driver, Tx Ch1
    03142:  Assert TR_SPI bit, Enables Tx
    03406:  Set LNA bias current to 0x6  
    0363E:  Set Tx VGA bias to 0xF and Tx Vector Modulator Bias to 0x6   
    01C7F:  Set Tx channel 1 gain to max – 10 dB (10 dB attenuator is enabled)
    02036:  Set Tx channel 1 Vector Modulator I vector   
    02136:   Set Tx channel 1 Vector Modulator Q vector ~ 45 degrees
    02802:  Load Tx override   
    02800:  Clear register
    03140:  Tx enabled; everything else default value: TR_SOURCE = 0 (T/R control is via TR_SPI bit) & TR_SPI = 0 (part is in receive mode)
    03040:  Assert Bias_CTRL bit
    02950:  Set external PA1 bias ON value to 0x50
    02A00:  Set external PA2 bias ON value to 0x00
    02B00:  Set external PA3 bias ON value to 0x00
    02C00:  Set external PA4 bias ON value to 0x00
    02D00:  Set external LNA bias ON value to 0x00
    00000: Disable SDO
    03860: Assert Beam RAM bypass and Bias RAM bypass bits


    With the 0x03140 you enable the tx subcircuits, but then set the TR_SPI bit to zero, which puts the part into receive mode, i.e. the PAx Biases will pull from their OFF value registers Reg. 0x46 through 0x49.  It doesn't look like you wrote to those registers so they will still have their default value of 0x00, which is 0V output. 

    For a quick test, you could keep all writes the same and do one additional write:0x04650.  You should see -1.5V on PA1 Bias now, given the part is in Rx mode and the OFF value is set to 0x50. 

    I would also do the 0x03860 write a lot earlier in the sequence if you want to pull the gain, phase and bias from the working registers.

  • Hi,

    Thanks for your reply. I have tried your suggestion of writing the OFF value registersa and writing 3860 earlier, but no luck. I feel the SPI communication itself is not happening with the ADAR. I tried reading back some RO registers like PRODUCT_ID, VENDOR_ID etc but I dont get anything back. I enabled the SDO before trying (by writing 0x000018). 

    May sound stupid but just to confirm, you asked me to write 0x004650 right? I mean 24bits and not 20 bits. All the data above, I am writing a leading 0 with it. I suppose thats how it should be.

    This is the spi driver output for writinh 0x03860 for eg:

    root@zynq:~# spidev_test -p \\x00\\x38\\x60 -v -D /dev/spidev32766.0
    spi mode: 0x0
    bits per word: 8
    max speed: 500000 Hz (500 KHz)
    TX | 00 38 60 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ | .8`
    RX | FF FF FF __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ | ...

    I still think am missing something basic, these are the steps I did right now:

    1. Power up the board, SDP connector left unconnected.

    2. Connected 4 wires from my zynq fpga GPIO to the 4 SPI lines on P3 connector on the eval board

    3. Started writing the above sequence of register writes

    4.. Checked and verified each write on oscilloscope by probing the SPI lines on connector P2.


  • 0
    •  Analog Employees 
    on Apr 24, 2019 6:41 PM over 1 year ago in reply to gensysco

    Sorry, I meant 24 bits.  Writes to the DUT should have the first bit Low.

    I would probe on P6, as that is connected to the actual DUT:

    Pin1 is CSB

    Pin3 is SDIO

    Pin 5 is SDO

    Pin 7 is SCLK

    If you don't see any SPI writes on P6 there is probably something wrong with the level translators.

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