I tried to give the eval board (EV-ADF4007EBZ1) two RF signals (square wave), one way as a REFIN, one way is RFIN. At the PFD, REFIN /2 is being compared to RFIN /8 .
For graph 1, REFIN = 12 MHz. RFIN =48 MHz. At the PFD, 6MHz(REFIN) is being compared to 6.25 MHz (RFIN).
For graph 2, REFIN = 12 MHz. RFIN =40 MHz. At the PFD, 6MHz(REFIN) is being compared to 5.25 MHz (RFIN).
Compared to graph 1, I found that when the REFIN frequency is higher than RFIIN, the CP output moved up 5V.
Can they post the question in English?
From the pdf it looks like they monitor the CP signal while varying the RF input frequency. The PLL is open loop so they will always get an ac signal…
Hi, i am the group member of Ning.
Here is a test and question description in Chinese.
Please give us some advice.问题咨询 - 测试ADF4007评估板.pdf
Thank you very much !
Do you think you could help on this one?
From the pdf it looks like they monitor the CP signal while varying the RF input frequency. The PLL is open loop so they will always get an ac signal on CP. When the RF input frequency equals the reference (100MHz) the CP signal is a steady 100 MHz signal with the pulse width equal to the phase difference between reference and RF input. When the RF input is set to 95 MHz but the reference is 100 MHz the CP ac signal pulse width increases until cycle slips occurs every 1/(100 MHz - 95 Mhz)= 0.2us.
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Thank you for your reply.
We are very sorry to have described our questions in Chinese.Now we describe questions in English.PDF
Please give us some advice.