Hello,

I am using the ADIsimPLL for the first time to simulate the ADF4007.
Question 1: The output frequency defines the reFference frequency so that there is no frequency error or phase error between them.As show in Fig.1, why is the time domain result showing a lock on phase and frequency when there is no error?
Question 2: As show in Fig.2,The phase detection output is always negative, and the error result will deviate more and more from zero?

Thanks,

Ning

Fig.1                                                                                                                         Fig.2

Parents
• Switching the Op-Amp from OP27 to ideal removes the frequency error.

This is basically the bias current of the op-amp. Lower bias currents give lower frequency error.