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Using a PLL chip as a phase detector


I would like to phase lock a stand-alone 100 MHz OCXO to an external reference signal that, depending on the user, can be anywhere from 100 MHz to 12 GHz.

OCXO Characteristics:

  • Exceptionally low-noise 100 MHz sine wave output (Wenzel Citrine series OCXO).
  • Electrical tuning range of +/- 20 Hz for a voltage of -/+ 5 VDC, so a gain of -4 Hz/V.
  • Unspecified tuning bandwidth, but let's assume it's on the order of 100 Hz or less.

RF Reference Characteristic:

  • Ultra-low noise, exceptionally low drift (phase stabilized) CW sine wave signal.
  • Frequency anywhere from 100 MHz to 12 GHz depending on the machine (it's the reference signal of a particle accelerator).

Design Requirement:

  • I would like to phase lock the 100 MHz OCXO to the RF Reference signal.
  • The RF Reference will be drifting slowly (if at all) and I want to track only this drift.
  • I absolutely don't want to introduce phase noise on the OCXO output by modulating its tuning input too much.

The design I envision uses a low-noise Fractional/Integer-N PLL chip, like the HMC704, as the phase detector. It can handle frequencies up to 8 GHz on it's VCO (RF) input. A prescaler, like the HMC862, will be placed in front of the HMC704 for frequencies higher than 8 GHz. The REF input of the HMC704 can take sine wave inputs up to 350 MHz, so the 100 MHz OCXO output is in a good range and has a slew rate in excess of 0.5V/ns. The dividers and precision counters in the HMC704 should allow sufficient flexibility to run the phase detector with, say, 50 MHz input signals and the charge pump should produce a current that varies with the phase difference between these two signals.

The charge pump current is then converted into a voltage and low-low-low pass filtered. A that point it can be made to drive the OCXO tuning input (using a bi-polar op-amp), but what I plan to do is just read the CP output voltage with a high precision ADC which through a FPGA or micro-controller drives a very low-noise, low glitch, DAC which in turn drives the OCXO tuning input through a low-noise, low drift, bipolar op-amp.

My question is: Is this OK, or is it totally the wrong approach? I have never seen a PLL chip used as a simple phase detector - but I have also not seen a phase detector that can compare a 100 MHz signal on one side with a 8 GHz signal on the other.

Any advise or suggestions would be much appreciated.

Thank you,