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Using a PLL chip as a phase detector


I would like to phase lock a stand-alone 100 MHz OCXO to an external reference signal that, depending on the user, can be anywhere from 100 MHz to 12 GHz.

OCXO Characteristics:

  • Exceptionally low-noise 100 MHz sine wave output (Wenzel Citrine series OCXO).
  • Electrical tuning range of +/- 20 Hz for a voltage of -/+ 5 VDC, so a gain of -4 Hz/V.
  • Unspecified tuning bandwidth, but let's assume it's on the order of 100 Hz or less.

RF Reference Characteristic:

  • Ultra-low noise, exceptionally low drift (phase stabilized) CW sine wave signal.
  • Frequency anywhere from 100 MHz to 12 GHz depending on the machine (it's the reference signal of a particle accelerator).

Design Requirement:

  • I would like to phase lock the 100 MHz OCXO to the RF Reference signal.
  • The RF Reference will be drifting slowly (if at all) and I want to track only this drift.
  • I absolutely don't want to introduce phase noise on the OCXO output by modulating its tuning input too much.

The design I envision uses a low-noise Fractional/Integer-N PLL chip, like the HMC704, as the phase detector. It can handle frequencies up to 8 GHz on it's VCO (RF) input. A prescaler, like the HMC862, will be placed in front of the HMC704 for frequencies higher than 8 GHz. The REF input of the HMC704 can take sine wave inputs up to 350 MHz, so the 100 MHz OCXO output is in a good range and has a slew rate in excess of 0.5V/ns. The dividers and precision counters in the HMC704 should allow sufficient flexibility to run the phase detector with, say, 50 MHz input signals and the charge pump should produce a current that varies with the phase difference between these two signals.

The charge pump current is then converted into a voltage and low-low-low pass filtered. A that point it can be made to drive the OCXO tuning input (using a bi-polar op-amp), but what I plan to do is just read the CP output voltage with a high precision ADC which through a FPGA or micro-controller drives a very low-noise, low glitch, DAC which in turn drives the OCXO tuning input through a low-noise, low drift, bipolar op-amp.

My question is: Is this OK, or is it totally the wrong approach? I have never seen a PLL chip used as a simple phase detector - but I have also not seen a phase detector that can compare a 100 MHz signal on one side with a 8 GHz signal on the other.

Any advise or suggestions would be much appreciated.

Thank you,


  • Something like...

    The controller must set N  to match the desired VCO frequency. Keep in mind there is a minimum N  restriction (20 in frac-N mode).  This means for VCO  frequencies <4GHz  you must increase R>1.    The biggest problem is increased phase noise at VCO frequencies < 2GHz.  The HMC704 has a  FOM of -227 dBc/Hz  but this degrades 3dB for every octave less than 2GHz.  At 100 MHz the HMC704 noise will increase by 15 dB  - maybe not a concern since this only applies inside the loop BW.  The only other concern is adding a monitor point at the VCO tune port may cause additional noise.

    The ADF41513 or ADF4159 can perform the same function without the divide-2 prescaler.

  • That's close, except I don't have a VCO that I can control. What I have in place of the VCO is an independent source (that can be anything from 100 MHz to 12 GHz) that I have no control over. Fortunately this source is phase stabilized and very low drift.

    What I want to do is drive the tuning input of the 100 MHz OCXO itself to make it track the source that is driving the VCO inputs of the HMC704. Essentially the picture you have above, except that the output of the op-amp (or 'monitor' signal) drives a tuning input of the 100 MHz crystal. The 'VCO' block is completely independent and can not be controller - only tacked.

    The tuning input of the 100 MHz OCXO is very low gain (4 Hz/V) and very low bandwidth (less than 100 Hz, likely around 10 Hz). What I am considering is turning the CP current directly into a voltage with a resistor, then low-pass filtering that voltage with an op amp and monitoring its output with a ADC. A very low noise, low glitch DAC will be used to drive the OCXO tuning input. Between the ADC and the DAC will be a FPGA that can be programmed to provide any sort of PID functionality and also extra filtering.

    Can the HMC704 be used in such a configuration or is it impractical? Is there a better approach?



  • Hi Tony

    Sorry for the delayed response.  Here's an updated picture.  I don't see anything wrong with this approach.  Just keep in mind with such a narrow loop BW you will get lock times in the 5 second range.  You must still respect the minimum N=20 restriction with frac-N operation.  As your "reference" drops below 2 GHz you need to reduce R.

    I guess the whole point is to monitor the actual frequency of the 100M to 12G equipment? Why not just pass it through a divider like HMC983 and count the pulses over a long time period.  Increase the  count time to improve the accuracy of the measurement.  Then you woundn't have to deal with a PLL, 100M source and  the ADC conversion of the monitor signal .

    You can email me directly at