AD9874 PLL loop filters design

Hi.

I intend to use AD9874 in an HF radio receiver.
Unfortunately, I could not design the loop filters of LO PLL and Clock PLL for AD9864, because ADIsimPLL does not provide its model in the list. Could you help me to carry out the design?

I attach my circuit diagram nearby AD9874.
I have to decide the following; R35, C70, C71, R34, C77, R37, C78, R38, C79.

Thank you your cooperation in advance.

Ryoji

Reference clock frequency: 12.288 MHz
IF input frequency: 69.408 to70.636 MHz

LO PLL Synthesizer
2nd IF frequency: 3.072MHz
LO frequency: 66.336 to 67.564 MHz (the devide-by-2 output of the VCO)
PFC frequency: 4 kHz

Clock PLL Synthesizer
Clock frequency(fclk): 24.576 MHz
PFC frequency: 12.288MHz