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AD9874 PLL loop filters design

Hi.

I intend to use AD9874 in an HF radio receiver.
Unfortunately, I could not design the loop filters of LO PLL and Clock PLL for AD9864, because ADIsimPLL does not provide its model in the list. Could you help me to carry out the design?

I attach my circuit diagram nearby AD9874.
I have to decide the following; R35, C70, C71, R34, C77, R37, C78, R38, C79.

Thank you your cooperation in advance.

Ryoji

Reference clock frequency: 12.288 MHz
IF input frequency: 69.408 to70.636 MHz

LO PLL Synthesizer
2nd IF frequency: 3.072MHz
LO frequency: 66.336 to 67.564 MHz (the devide-by-2 output of the VCO)
PFC frequency: 4 kHz

Clock PLL Synthesizer
Clock frequency(fclk): 24.576 MHz
PFC frequency: 12.288MHz

  • ad1/ LO PLL

    I found datasheet of VCO: V135ME01-LF. Tuning sensitivity is 22MHz/V. VCO frequency = 134MHz. I took charge pump current 2*0.67mA=1.3mA and loop BW=100Hz. I assume phase margin = 45Deg. Then C77=1uF, C78=5.6uF, R37=750R, R38=1K0, C79=56nF. Is really U5A necessary?

    ad 2/ CLK Synth

    VCO tuning sensitivity is unknown. You shall measure it.

  • Thank you for your quick and helpful reply.

    About LO PLL, I found an online loopfilter calculator, which provides same results as yours.
    www.changpuak.ch/.../pll_loopfilter_calc.php

    About CLK PLL, I will measure the VCO tuning sensitivity using an evaluation board EVAL-AD9874 after I get it.

    I appreciate your advice.

    Ryoji

  • Hello,

    Components below could be used to implement your CLK OSC tuned for 24.576 MHz. 

    Regards.

  • Thank you for your suggestion. It's great help for me.

    I'd like to confirm some points.

    1) In your design, is the bias current setting supposed to be 0.4 mA ?

    2) As VDDC is 3.3V in my case, do I have to adjust the component values ?

    3) Could you tell me how you calculate the component values in your design ?

    I appreciate your kind answer.

    Ryoji

  • Hello,

    Answers to your questions are as follows:

    1) One should select RBIAS so that the common-mode voltage at CLKP and CLKN is approximately 1.6 V.  Based on a 3.3 supply with desired IBIAS setting of 0.65 mA........RBIAS= (3.3-1.6 V)/0.65 mA =2.61 kohm. Closest value should suffice.  If lower IBIAS setting is desired for power savings..........just replace 0.65 mA with other possible IBIAS setting.

    2) Only RBIAS needs to be adjusted.

    3) The 0.82 uH inductor along with series 68 pF and varactor (1SV228) for an LC tank with resonant frequency being equal to 1/(2pi*sqrt(LC)).   The equivalent capacitance is equal to 0.68 pF*CVAR/(0.68 pF+CVAR).  Value of CVAR depends on component transfer function of CVAR vs Vdc with Vdc being filtered charge-pump output appearing across varactor.

    Note........while equation gets one close to correct values, typically one needs to experiment to get COSC value correct such that the Vdc bias voltage in normal operation is around mid-range of the charge-pump output range.

    Regards.

  • Hello,

    Thank you for your reply.

    I'm preparing a prototype board and will experiment next March.

    Thank you for your cooperation.

    Regards,

    Ryoji