Request to confirm the logic levels for ADAR1000

Hi team,

1. We are planning to use ADAR1000 and we are looking to FPGA interface requirements during that all control interfaces from FPGA used for ADAR1000 are logic 1.8V except PA_ON pin where this signal is pulled up with AVDD3 so assuming that logic level will be LVTTL. Kindly confirm the same.

2. In THEORY OF OPERATION, circuit shown for Amplifier Bias, TR_SW_NEG, TR_POL Switch Driver at figure 81 and figure 82 protection diode is shown for positive rail. So from this we inferred that the output signal will varry from 1.8V to -5V or 0 to -5V.


Krishna Phani M