I'm planning using the DIVOUT of ADF4360-9 to clock an ADC. From the figures the data sheet shown, it seems the out is only about 1.5V when the output duty cycle is not 50%. Can someone confirm me that if use the A/2 mode, the DIVOUT will be standard CMOS level at any frequency?
Yes, the DIVOUT is not very well specified…
If you look at the signal swings on page 9, in fig 12, the swing from high to low is greater than the required 1.2Volts, but the duty cycle is only 45%, therefore , if the application requires the o/p to have a duty cycle of close to 50%, then you will need a buffer at the higher frequencies…regards Brigid.