Using 16 ADAR1000 chips to make 8x8 X phased array, need info how do I control each RX and TX of each ADAR1000 using single controller.

Hello Jdobler,

I'm looking for Timing diagram of Transmit and Receive Mode switching, i.e, PA_Bias and LNA_Bias, Ramp up timings, delay 1 and delay 2. PA_Bias voltage, -4.8V to -2.5V, time delay for this value and same for the LNA Bias

Does this DELAY 1 and DELAY 2, more than 50ns? Please confirm this as earliest as possible, it's a critical issue for my current project.

Expecting a quick response from you guys.

Thanks in advance.

DELAY1 and DELAY2 are set in Registers 0x4B and 0x4C, Tx to Rx and Rx to Tx, respectively. 

Both delay times are relative to the period of SCLK. 

Minimum delay is with the 4-bit nibble (in said registers) set to 0x0.  Maximum delay is nibble set to 0xF.

Delay = Nibble_Value * T_SCLK

If you had a 20 MHz SCLK, with a period of T_SCLK = 50ns the min and max delays would be:

• Min Delay = 0 ns
• Max Delay = 15 * 50 ns = 750 ns

Gate biases can be driven by the following pins (pin attributes in parentheses):

• PA_BIAS1/2/3/4 (0V to -4.8V; +/- 10mA)
• LNA_BIAS (0V to -4.8V; +/- 10mA)
• TR_SW_NEG (0V to -5V; +/- 1mA)
• TR_SW_POS (0V to +3.3V)
• TR_POL (0V to -5V; +/- 1mA)

You can decide how to connect these pins to your T/R module, depending on its biasing needs and your project requirements.

Hi jdobler, could you tell me the reason, why the ADAR1000 has 16 address bits? Would it not be possible with less address bits?

And there were also a hint for the gain in the datasheet....for example for maximum gain 127...actually there is no detailled explanation how this normalized gain assembled..

Having 16 address bits is standard ADI SPI protocol.  We actually do end up using a large amount of the address space with the RAM.  Also remember that there are 2 chip address bits AD0 and AD1, that are in bit positions [14:13] in the address header. 

The maximum gain is normalized to 0 dB at each frequency plotted to show that the gain vs. VGA gain code transfer function is the approximately the same for any frequency. 

Actual gain can be seen on the gain vs. frequency (over all gain codes) in Figures 9 & 28.

But actually I am asking myself how many addresses the ADAR1000 actually has? If you really need 16 bits you have to have endless amount of addresses....

Yes, if all 16 bits were used for register addressing, that would be quite a lot, about ~65k registers.

But not all of the 16 address bits are used for register address space.  Indexing the 16 addressing bits from 0 to 15, we use:

• Bit 15 (MSB) for the read/write indicator bit
• Bits [14:13] for the chip address bits
• Bits [12] for RAM addressing (more on this below)
• Bits [11:0] for register addressing

So there is only 0x0000 through 0x0FFF available registers, or 4096.  Not all of the possible 4096 registers are used.

RAM addressing starts at 0x1000 and ends at 0x1FFF.  Another 4096 addresses available to write to.  So in total there are only 8192 addresses available between the registers and RAM. 

Hopefully, this clears up any confusion. 

Yes, if all 16 bits were used for register addressing, that would be quite a lot, about ~65k registers.

But not all of the 16 address bits are used for register address space.  Indexing the 16 addressing bits from 0 to 15, we use:

• Bit 15 (MSB) for the read/write indicator bit
• Bits [14:13] for the chip address bits
• Bits [12] for RAM addressing (more on this below)
• Bits [11:0] for register addressing

So there is only 0x0000 through 0x0FFF available registers, or 4096.  Not all of the possible 4096 registers are used.

RAM addressing starts at 0x1000 and ends at 0x1FFF.  Another 4096 addresses available to write to.  So in total there are only 8192 addresses available between the registers and RAM. 

Hopefully, this clears up any confusion.