Using 16 ADAR1000 chips to make 8x8 X phased array, need info how do I control each RX and TX of each ADAR1000 using single controller.

Hello,

I'm trying to make 64 elements phased array(8 x 8) using 16 ADAR1000. 

I'm using TR module. I want to control each RX and TX (64 RX and 64 TX) individually through SPI. I'm unable to find information regarding this. If any document regarding this, it will be helpful, and also if I get info regarding hardware (schematics) will be much helpful.

I hope I will get reply ASAP.

Thanks in advance.

Regards,

Vinayak



Can I control each RX and TX via SPI?
[edited by: chabbivinayak at 8:08 AM (GMT 0) on 4 Jan 2019]

Top Replies

Parents Reply
  • 0
    •  Analog Employees 
    on Nov 11, 2019 3:59 PM 11 months ago in reply to MarkList

    Having 16 address bits is standard ADI SPI protocol.  We actually do end up using a large amount of the address space with the RAM.  Also remember that there are 2 chip address bits AD0 and AD1, that are in bit positions [14:13] in the address header. 

    The maximum gain is normalized to 0 dB at each frequency plotted to show that the gain vs. VGA gain code transfer function is the approximately the same for any frequency. 

    Actual gain can be seen on the gain vs. frequency (over all gain codes) in Figures 9 & 28.

Children
  • But actually I am asking myself how many addresses the ADAR1000 actually has? If you really need 16 bits you have to have endless amount of addresses....

  • 0
    •  Analog Employees 
    on Nov 11, 2019 8:58 PM 11 months ago in reply to MarkList

    Yes, if all 16 bits were used for register addressing, that would be quite a lot, about ~65k registers.

    But not all of the 16 address bits are used for register address space.  Indexing the 16 addressing bits from 0 to 15, we use:

    • Bit 15 (MSB) for the read/write indicator bit
    • Bits [14:13] for the chip address bits
    • Bits [12] for RAM addressing (more on this below)
    • Bits [11:0] for register addressing

    So there is only 0x0000 through 0x0FFF available registers, or 4096.  Not all of the possible 4096 registers are used.

    RAM addressing starts at 0x1000 and ends at 0x1FFF.  Another 4096 addresses available to write to.  So in total there are only 8192 addresses available between the registers and RAM. 

    Hopefully, this clears up any confusion.