I am trying to program to on-chip SRAM
The description in the manual is quite confusing.
Would you please show some examples to program on-chip SRAM?
1. Rx channel setting
1) Rx channel 1 : phase = 0 degree, relative amplitude : -3 dB
2) Rx channel 2 : phase = 45 degree, relative amplitude : 0 dB (max gain)
3) Rx channel 3 : phase = 90 degree, relative amplitude : 0 dB (max gain)
4) Rx channel 4 : phase = 135 degree, relative amplitude : -3 dB
2. Tx channel setting
1) Tx channel 1 : phase = 0 degree, relative amplitude : -3 dB
2) Tx channel 2 : phase = 45 degree, relative amplitude : 0 dB (max gain)
3) Tx channel 3 : phase = 90 degree, relative amplitude : 0 dB (max gain)
4) Tx channel 4 : phase = 135 degree, relative amplitude : -3 dB
I can not understand clearly the below sentence from the datasheet.
Would you please explain it with some example?
For example, if I have 9 beams are configured in the memory, how can I control the beam sequence using SPI?
In this case, the settings for each receive channel are loaded by writing to Register 0x03D through Register 0x040, and for each transmit channel by writing to Register 0x041 through Register 0x044. The BEAM_RAM_ BYPASS bit in Register 0x038 determines where the amplitude and phase settings are pulled from the memory (low) or written to over the SPI (high).
Apologies for the lack of information. The RAM access explanation in the datasheet is poor, and there is not a programming example to reference in the current datasheet. I'm currently working on a revision that will include these things. In the meantime, there is some pertinent information:
Here is an example sequence of Writes, given the settings you have provided above and I'm still assuming ADDR1 and ADDR0 are pulled low. Also, for a normalized max gain of 0 dB, this corresponds to a gain code of 127 (0x7F) and -3 dB down is about a gain code 100 (0x64).
//Write to the Memory locations themselves; we are writing just one beam's worth of info for Tx and Rx
//Set the BEAM_RAM_BYPASS bit to low
//Rx Memory Writes
0x100064 //Rx Chan1, attenuator and VGA gain
0x10013F //Rx Chan1, I VGA gain and polarity bit
0x100220 //Rx Chan1, Q VGA gain polarity bit
0x10047F //Rx Chan2, attenuator and VGA gain
0x100536 //Rx Chan2, I VGA gain and polarity bit
0x100635 //Rx Chan2, Q VGA gain polarity bit
0x10087F //Rx Chan3, attenuator and VGA gain
0x100921 //Rx Chan3, I VGA gain and polarity bit
0x100A3D //Rx Chan3, Q VGA gain polarity bit
0x100C64 //Rx Chan4, attenuator and VGA gain
0x100D16 //Rx Chan4, I VGA gain and polarity bit
0x100E35 //Rx Chan4, Q VGA gain polarity bit
//Tx Memory Writes
0x180064 //Tx Chan1, attenuator and VGA gain
0x18013F //Tx Chan1, I VGA gain and polarity bit
0x180220 //Tx Chan1, Q VGA gain polarity bit
0x18047F //Tx Chan2, attenuator and VGA gain
0x180536 //Tx Chan2, I VGA gain and polarity bit
0x180635 //Tx Chan2, Q VGA gain polarity bit
0x18087F //Tx Chan3, attenuator and VGA gain
0x180921 //Tx Chan3, I VGA gain and polarity bit
0x180A3D //Tx Chan3, Q VGA gain polarity bit
0x180C64 //Tx Chan4, attenuator and VGA gain
0x180D16 //Tx Chan4, I VGA gain and polarity bit
0x180E35 //Tx Chan4, Q VGA gain polarity bit
//Write the Beam Position 0 into the RAM index registers and set Fetch bit
0x3D80 //Rx Chan1
0x3E80 //Rx Chan2
0x3F80 //Rx Chan3
0x4080 //Rx Chan4
0x4180 //Tx Chan1
0x4280 //Tx Chan2
0x4380 //Tx Chan3
0x4480 //Tx Chan4
Provide 6 or more additional clock cycles to load in the new settings from memory.
//Perform a LD_Rx or LD_TX, via the pins or the SPI (Reg 0x28), for the new setting to take effect; assuming a SPI
0x2801 //For Rx load
0x2802 //For Tx load
I'll attach some extra documentation that will be helpful for decoding Table 7.
Hi, sir. I also have problems on this topic. I finished the TX/RX control over SPI just following the ADAR1000 user guide.
Recently, I am trying the TX/RX control over memory access. So I found this discussion.
The platform I used is ADAR1000-EVALZ board. I write the sequential setting in a text file, and load to write from the official GUI tool. The above example code I used directly or did some modification, it both didn't work for my settings.
Simplify the control setting to one TX channel, TX channel 1. The following is my whole code of text file:
0x00099 // reset all setting
0x03616 // TX bias current
0x03706 // TX bias driver current
0x03800 // use the beam position setting (RAM)
0x02F7F // enable TX subcircuits
0x180064 // TX Chan1, attenuator and VGA gain
0x18013F // TX Chan1, I VGA gain and polarity bit
0x180220 // TX Chan1, Q VGA gain polarity bit
0x04180 // TX Chan1 loads the beam position 0
0x02802 // TX load
Did I lose something?
If you want to source the bias settings from the control registers, you'll need to assert the BIAS_RAM_BYPASS bit in Reg 0x38, so write 0x3820, instead of 0x3800.
Else you'll need to write the bias settings into memory (which are all zeros by default). See Tables 8 through 11 in the datasheet.
Thank you, sir. That gives me a big help. I've solved my problem!