I'm using the LTC6946-1 to output a 2.5 GHz clock.
The LTC6946-1 only locks sometimes when using an open-loop bandwidth of 1440 kHz (with Fpfd = 163840 kHz). This should work (according to datasheet and PLLWizard) since the open-loop bandwidth is 11 times lower than Fpfd.
The LTC6946-1 always locks if I lower the open-loop bandwidth to 130 kHz.
I can use an open-loop bandwidth that is less than 1440 kHz, but I want to be sure that the LTC6946-1 always will lock. How can I make sure that my chosen bandwidth will work? Can it be simulated or calculated or do I have to experiment some and then back off?
My settings: Fref: 16.384 MHz Fstep: 16.3840 MHz Frf: 2490.368 MHz R div: 1 N div: 152 O div: 1 FILT: 3 LKWIN: 3 ns B cnt: 24 Icp: 11.2 mA
Hello, Thanks for taking the time to reach out and ask this question.
Do you mind if I ask what specification is driving the wider loop bandwith?
PLLWizard should be able to simulate this. Can you forward the loop filter values for the 130kHZ and the 1440kHz you are using? Also, can you send me the reference part number (or phase noise curve)? This will help me set up a simulation similar to closer to what your setup is. Are you using the LTC6946 demo board? What power supplies are you using?
Below are the values I calculated with PLL wizard and its resulting phase margin for the 1440 kHz loop filter (ideal values). Are these the values you are coming up with? Ideal you want >45 degrees phase margin for loop stability, the below loop filter is showing 58 degrees phase margin (plot on the right). For phase margin read the blue curve value where the red curves zero crossing is located.
A couple things to try
- When the capacitor values are in the pF range (i.e. Cp is 40pF), PCB parasitics can start to have an affect on the loops actual capacitance. One thing I have done in the past is to double the Ci value(i.e. try 1nF), or halving Cp (i.e.22pF), or both. This has the affect of increasing phase margin. The Phase noise curve can change slightly. Loop BW should stay the same.
- Wide bandwidths are more susceptible to noise. The two big noise sources are reference noise and power supply noise. Avoid switching power supplies. Its possible a spur from a switching supply is causing you some issues. We developed a demo board DC2429 to clean up lab supplies spurs. It uses the LT3042 LDO, which is the best LDO I know of to clean up power supply noise and spurs.
- Capacitor selection. If you can use COG (or NP0) capacitors your loop filter will not be sensitive to micro-phonics (vibrations). X7R, X5R caps are sensitive to vibrations. In other words if your board is shaking slightly a micro-phonic issue to lose lock. You can tap your board with your finger and see it loses lock. I don't think this is what is going on with your setup, but it is a best practice to follow. One less thing to worry about.
-You might see if setting LTC6946 CPCHI and CPCLO bits to the high state helps.
Hi and thanks for your prompt and very thorough answer.The design is quite large and I must admit that I didn't spend enough time on the LTC6946. I designed the loop filter with a previous design in mind, and for that design it was best to use a wide bandwidth.1440 kHz loop filter gives me:Rz: 848 ohmCi: 0.46 nFCp: 0.04 nF130 kHz loop filter gives me:Rz: 76 ohmCi: 56 nFCp: 4.6 nFThe oscillator I'm using is a Taitien TCETBIS-NF-16.384MHz (clipped sine wave output). I set BST=1 since the swing is about 1.4 V. Its phase noise is:100 Hz: -115 dBc/Hz1 kHz: -135 dBc/Hz10 kHz: -148 dBc/HzThe oscillator and the LTC6946's VREF+ and VRF+ is supplied via an LDO. Ferrites exists on both the input and the output of the LDO. This should give optimal attenuation of both low and high frequency noise.The LTC6946's VD+, MUTE and VREFO+ are connected to unfiltered 3.3 V. REFO is not used in our application.The LTC6946's VVCO+ is supplied via a switching regulator but is filtered using a ferrite. VCP+ is connected to VVCO+ via a 15 ohm series resistor. I'm not using an LDO for the 5 V due to cost and PCB real estate optimization.I will try to connect the 5 V to a noise free supply and see if that helps.I have measured with an oscilloscope on CP/TUNE when my LTC6946 won't lock. What I see is something similar to a saw tooth with maximal swing at a few MHz. If you want I can share a screenshot.
In general for all the PLL/VCO's like the LTC6946 (not just the LTC6946) the VCO and CP supplies are the most sensitive to switching supplies. The PLL/VCO reference supply, and the supply to the Taitien oscillator are also sensitive. It might be interesting to compare the TUNE waveform frequency to the frequency of the switching supply. Or you can see if a cleaner supply resolves the issue. Feel free to send your waveform. Even with the 130k loop filter, I bet the switching supplies are creating a spur in the output spectrum (although it will be attenuated quite a bit by the loop filter).
One other thing to look at is the DC votlages on the CMA, CMB, CMC, BVCO, BB and TB pins. These voltages should read CMx, TB = 2.3V, BB=1.23V, BVCO=5V. Let me know what you measure, that may tell me something.
That particular Taitien reference is limiting the inband performance of the LTC6946. I simulated the LTC6946 in PLLWizard with the phase numbers you provided and calculated the best loop filter (wrt integrated phase noise) to be in the 80kHz range. I simulated and provided results for 80k, 130k and 1440k loop filters with the Taitien oscillator performance below for reference. I would go with the 80k loop filter, unless you a really pressed for a faster settling time.
80kHz loop filter (integrated phase noise rms = jitter = 399ps)
80kHz loop filter (integrated phase noise = jitter = 411ps rms)
1440kHz loop filter (integrated phase noise = jitter = 934ps rms)
Below is a sceenshot from the oscilloscope on CP/TUNE when the LTC6946 does NOT lock.
CMx and TB reads about 2.25 V. BB reads 1.19 V I don't know which pin you are referring to when you ask about BVCO.
I connected the 5 V to an external supply. It looks like it helped but I'm not 100 % sure. Once it wouldn't lock even with the external supply. The external supply might however not be good enough.
Anyway, my solution will be to use a 130 kHz or 80 kHz open-loop bandwidth and filter the 5 V better.
May I suggest that you add some of this information to your article at https://www.analog.com/en/technical-articles/debugging-the-ltc6946-getting-the-pll-to-lock.html ?
Thanks. The bias voltages are reading correctly which is a good sign. Sorry about the BVCO pin reference, that refers to a pin on the LTC6948, not the LTC6946. If the switching supply (or something else on yoru board) was running at 1.3MHz(2.59M/2) that would be a good clue as to what could be causing this issue. Glad you are up and running.