We are planning to use your PLL part: LTC6948-4 for output frequency range of 5500 to 6350MHz output frequencies.
As per your datasheet from 1000 to 5800MHz recommended to use 68nH & 100pF capacitor for maximum output power and best phase noise performance.But for our frequency range of 5500 to 6350MHz the above said values will not meet SRF requirements. So we are planning to use 18nH (0402DC-18NXGRU) & 0.01uF (520L103KT16T) high SRF components. Is it okay for our above frequency range? What is the typical single-ended o/p power expected for the above values?
That is a mistake in our datasheet. The 68nH and 100pF capacitor is recommended up to 6.4GHz, refer to datasheet Figure 17(below). Originally our max frequency part was the LTC6948-3, which went to 5.8GHz. It looks like when we released the LTC6948-4 (6.4GHz) we forgot to update table 18. Good catch.
If you need more output power I would recommend using a diff to SE balun as shown in the datasheet. You may want to look at the TDK HHM1570B1 balun. 6.4G is out of its datasheet range, but has worked well for us in lab at that frequency.
This plot was made with the 68nH, 100pF values and should give you and idea of the output level vs temperature.
But the issue in using 68nH & 100pF at our frequency is SRF of these components.
Even if we use high frequency RF Inductor which is not supporting SRF upto our maximum frequency of 6350MHz with 68nH value.
We need to know this 68nH is used as choke only for high impedance to power supply line to RF or It has impedance matching with 100pF capacitor to make RF+ & RF- pins as 50 Ohms.
If only for high impedance supply feeding then Is there any issue by using 18nH (0402DC-18NXGRU) & 0.01uF (520L103KT16T) instead of 68nH & 100pF capacitors for our frequency range of 5500 to 6350MHz?
Did you faced any PLL output oscillations due to not proper impedance mismatch?
For LVCOMS, here are is the preferred schematic. Please ensure R-SER limits the CMOS current enough to not exceed the reference's absolute max output current condition. In this case 1.65V/150 ohms ~11ma. The AC-coupling cap centers the 3.3V square wave around GND (+/- 1.65V).
If I use 100Ohm Series resistor and 50Ohms shunt resistor my LVCMOS output swing voltage will be divided from 3.3Vp-p to 1.1Vp-p.
1. Is it OK for your proper PLL operation?
2. Also at the input of RSER resistor (LVCMOS output) should I need to use AC coupling capacitor? What is the purpose?
The schematic provided in my last reply is OK for proper PLL operation. The AC coupling capacitor between the CMOS output and RSER resistor helps to limit the current out of the CMOS output. If the capacitor is removed, then when the CMOS output is high, it will need 3.3V/150 ~22mA. If an AC-coupling cap is used than current is +/-1.65/150 ohms or +/-11mA. Many CMOS device have an absolute maximum output current spec. You will need to refer to the datasheet of your CMOS device to figure out what that spec is.
Thanks for your LVCMOS input clock reference suggestions.
We are unable to see any differential clock input recommendation like LVDS to REF+ & REF- pins.
Do you have any recommendation circuit?
Hi, We have another part called the LTC6951 which has a similar reference input structure to the LTC6948. We did a much better job in the LTC6951 datasheet making recommended schematics for the reference input. Below is the LVDS recommendation, but if you need to use another reference input signal type to the LTC6948 you can refer to the LTC6951 datasheet. I know this sounds odd.