Page 13 of the ADRF5730 device data sheet lists a power-up/power-down sequence. I am trying to gauge the importance of this sequencing. Is this presented only a recommendation or does the sequence, particularly the power-down sequence, absolutely need to be followed to prevent damage to the device?
If the power-down sequence must be followed, are there any specific timing requirements between the individual steps? How close can they be? Please advise. Thank you.
Sorry for the delayed response.
For our ADRF57XX attenuators and the ADRF50XX switches, the recommended power up sequence is VDD-VSS-Control-RF.Power down sequence is the reverse of the power up sequence: RF-Control-VSS-VDD.
The ideal power up sequence is VDD before VSS to avoid transient current draw on VDD. However, it is ok if VSS is powered on before VDD.
Powering VDD before controls:It is imperative that VDD is powered on before the control voltages. Failing to do so may inadvertently forward bias the ESD protection diodes between VDD and Control. The high current draw will damage these diodes and the switch/attenuator will not function.Also, a side note, some control pins do not have internal pull-up/down resistors. (Please refer to the interface diagrams in the datasheet.) These pins should not be left floating.
We are updating this information in the datasheets.
Regarding the control pins without internal pull-up/down resistors:
From the interface diagrams on the datasheet, it looks like D0, D1, and D2 have internal 100k pull-downs, meaning LE, PS, D3, D4, and D5 need external resistors.
Can you confirm?
We recommend using pull-down resistors to ground on LE, PS to hold these to a valid logic state.
When using the attenuator in parallel mode, we recommend pull down resistors to ground on D3, D4 and D5 for the same reason. In serial mode, D3/SEROUT is an output pin. This pin can be left open if SEROUT is not being used.