# Single tone signal generation at microwave frequency with best phase noise and spurious performance

Hello all.

What is the best way to generate a single tone signal with best phase noise and spurious performance?

Is frequency multiplication the best way? single stage multiplication or multi stage multiplication?

I want to produce a single tone 6 GHz signal with a 100 MHz Sine Wave OCXO by multi stage multiplication.

For best phase noise and spurious performance what issues are important to notice?

Best Regards.

Thanks.

Parents
• Each multiplication decreases the phase noise performance by factor 20*logN, where N is multiplication factor. In your case N=6GHz/100MHz=60. It means 20*log60=36dB. Depends on exact OCXO datasheet, but let assume typical value of noise floor -165dBc/Hz. It means the signal at 6GHz you can expect noise floor -126dBc/Hz (assuming 3dB degradation by multiplicator itself). I think it is quite poor performance. It means you would probably need additional narrow band filtering at 6GHz.

If you do multiplication in one stage, e.g. using comb line generator, you will see in the spectrum multiples of 100MHz: ...5.9GHz, 6GHz, 6.1GHz..., which need to be filtered out, except wanted 6GHz signal.

For the best preformace I recommend to build PLL. Multiplication of OCXO has been popular maybe 30 years ago.

Best Regards

• Thanks @viktor_vojta. Yes PLL is very good. But by the best PFDs with the best phase noise floor, as I know, such as HMC440 with about -150dBc/Hz phase noise floor for 100MHz input, the PLL output signal at near offsets in the loop bandwidth is limited to -150+20LogN. (Also HMC440 dont support N=60 but it is not hard problem because there is solution). So with PLL my phase noise at low frequency offsets in the loop bandwidth is limited. In my case -150+20Log60=-114dBc/Hz. I want -116dBc/Hz @1KHz. So PLL is not useful for me. I want about -116dBc/Hz @1KHz and about -155dBc/Hz at far offsets as floor. You said right, with multiplication far frequency offsets is too bad. But what is the solution? Thanks.

• Thanks @viktor_vojta. Yes PLL is very good. But by the best PFDs with the best phase noise floor, as I know, such as HMC440 with about -150dBc/Hz phase noise floor for 100MHz input, the PLL output signal at near offsets in the loop bandwidth is limited to -150+20LogN. (Also HMC440 dont support N=60 but it is not hard problem because there is solution). So with PLL my phase noise at low frequency offsets in the loop bandwidth is limited. In my case -150+20Log60=-114dBc/Hz. I want -116dBc/Hz @1KHz. So PLL is not useful for me. I want about -116dBc/Hz @1KHz and about -155dBc/Hz at far offsets as floor. You said right, with multiplication far frequency offsets is too bad. But what is the solution? Thanks.

Children
• FOM of selected HMC440 is -230dBc/Hz, which is quite good value. I think it would be hard to find commercial PFD with significantly better performance. You can use PFD for the initial locking and then under lock status an RF mixer (best passive) as a phase detector. Of course 100MHz shall have also appropriate spectral mask for your application. Please distinguish between phase noise outside the PLL-loop BW and inside PLL-loop BW. -155dBc/Hz at far offset ≡ outside PLL BW is practicable.

Regards

• Thanks . I said -116dBc/Hz @ 1KHz offset in the PLL bandwidth. And -155dBc/Hz @ 30MHz offset outside of the PLL bandwidth. How with mixer? Thanks.

• The phase noise outside the loop BW, -155dBc/Hz at 30MHz, is defined by VCO itself. Such value for VCO at fundamental frequency is OK. Thus the loop BW must be 1kHz<< loop_BW << 30MHz is you decide to build PLL. The mixer will of course degrade the performance, let assume by 3dB, but I never measured it. It means the requirement on the OCXO are : -116dBc/Hz -3dB -20log60 = -155dBc/Hz.

Regards

• Thanks . Above, in the pre-previous Reply, you said: "You can use PFD for the initial locking and then under lock status...". What do you mean?

• As you know any mixer can work as a phase detector. Of course you have to select such mixer, where IF starts from DC. You determine the compare frequency for the best performance, e.g. 600MHz. OCXO 100MHz will be multiplied by 6 and filtered and VCO divided by 10 using low noise divider. In case of PLL unlock status, the mixer output would be f.IF = f.LO - f.RF ≠ 0Hz ,where LO is divided VCO and RF is multiplied OCXO as an example. Thus the DC voltage is 0V. PLL is not able to lock, therefore you need frequency detector for initial phase, which tunes the VCO at 10*600MHz. As soon as the PLL is locked, you over-switch loop filter (in principle PI regulator) from frequency detector to mixer IF output. Because frequency detector is special case of phase-frequency detector, you may take PFD, it is a standard component, easy to get. PFD helps you in initial phase only, low noise feature is thus not necessary. During normal operation PI regulator will integrate phase differences between LO and RF ports and VCO stays locked. I think the phase difference LO-RF will be ~90Deg at the mixer during normal operation.

Regards