There is a register called ALARM address 0x1.What kinds of errors are indicated in this register? Are there shown errors on the SPI bus only?What is criteria to set bit 14 to "too fat error" and bit 13 to "too many errors"?Why it happends? What we can do with it?Could you please to provide the description of the Alarm register?
The Alarm registers in ADMV1013 & ADMV1014 are for customers to know if there are too many / or too few SCLK in one write.
For a single write the customer should have 24 sclk, in a case that there are more or less the alarm bits in register 0x01 will set high. Please keep in mind that in order to enable these bits register 0x02 “Alarm mask” need to be enabled.
We are using 32 cycles of sclk to drive admv1014 and we do get the too many sclk errors.
No matter Setting the mask bit to 0 or 1, we always get this too many error.
But we can write a bunch of registers and read back the correct values.
So, only one question, will this too many clock errors prevent the SPI shift register from loading into the actual register space.
In other word, even if we supply more clock cycles than the admv1014 need, are we still control the admv chip accordingly or it does not work if we supply 32 cycles of clock?
By the way, why we can not mask the too many sclk off, which is weird.
thanks a bunch