ADIsimFrequencyPlanner enables fast, accurate simulation and elimination of integer boundary spurs from Analog Devices PLL synthesizers. The tool analyzes the user's output requirements, and then optimizes the PFD frequency for each output step to give the best integer boundary spur performance. The optimum PFD frequency is selected by changing the output divider of the clock generation chip (e.g. HMC7044) and changing the reference input divider of the PLLVCO (e.g. ADF5355, HMC830).
Typical results are better than -100 dBc for integer boundary spurs across output frequencies from 55 MHz to 13.6 GHz.
Does it give you an error message? Either in normal or compatible mode?