HMC703 Cycle Slip Prevention

I am using the HMC703 PLL IC with the VCO function provided by HMC835. I notice that PLL settling is longer with Cycle Slip Prevention left ON, vs OFF; i.e pin15 of reg07 ='1' vs '0'.

The loop bandwidth is 100kHz; the settling time is <35usecs, CSP OFF, and >47usecs CSP ON. Can anyone offer a possible explanation??

My understanding is CSP is not necessary with a switched bank VCO like HMC835; however, it is a big surprise that leaving it enabled SLOWS down the settling time. 

    •  Analog Employees 
    on Oct 16, 2020 9:12 AM 1 month ago

    Hi Des,

    If you simulate your design in ADisimPLL, then on the left go to Chip>Phase Detector there is a CSP enable control. This will give you an idea if CSP will be useful to reduce lock time in this scenario.

    To enable CSP, the reg7[15] bit should be set as you have it but can you also confirm that reg7[21] = 1 for CSP.

    Other than this, the LD trainer timer sequence must be executed correctly. First set LD trainer bit (reg7[20]) low. Then ensure the reference is applied and R divider is set correctly for your configuration. Then bring the LD trainer bit (reg7[20]) high. 

    After this, the LD trainer can be re-ran any time after the reference/R divider are set by toggling reg7[20] low then high (it's rising edge activated)

    If this doesn't help, could you repeat the experiment with CP current reduced and then at its lowest setting.

    Regards,

    Alex

  • I ran ADISimPLL with CSP ON vs OFF. With it ON, the transient settled 2usecs faster than with it OFF – 34us vs 36.5usc.

     

    Repeatedly measuring settling time by pinging back and forth between 2 frequencies – there is approx. 2-3 usec variation with CSP OFF around an average=34usecs, but with CSP ON, there is are significant outliers - > 47usecs happening  approximately once every 100 times. The bulk of the times with CSP ON are the same as CSP OFF.

     

    We do not execute the LD training sequence described. Could it explain the observed behavior?

    •  Analog Employees 
    on Oct 23, 2020 11:50 AM 1 month ago in reply to Des_coghlan

    I agree that the CSP shouldn't increase the lock time as much as your seeing, assuming it's configured right and your design allows it.

    It's important to ensure the LD window is set up correctly and the training sequence is used. You can send me your register writes and some details on your circuit over email and I could check them if you want

    Regards,

    Alex