I am using the HMC703 PLL IC with the VCO function provided by HMC835. I notice that PLL settling is longer with Cycle Slip Prevention left ON, vs OFF; i.e pin15 of reg07 ='1' vs '0'.
The loop bandwidth is 100kHz; the settling time is <35usecs, CSP OFF, and >47usecs CSP ON. Can anyone offer a possible explanation??
My understanding is CSP is not necessary with a switched bank VCO like HMC835; however, it is a big surprise that leaving it enabled SLOWS down the settling time.