In this blog we will demonstrate a typical direct conversion I/Q receiver application using slightly modified LTC5594 and AD9208 evaluation boards. The test circuit is shown below in Figure 1. For simplicity, only the I-channel is shown. The Q-channel is identical.
Figure 1. LTC5594 + AD9208 Evaluation Board Test Circuit
On the standard LTC5594 Evaluation board (DC2645A), capacitors C9-C12 and inductors L1-L2 form a 1GHz bandwidth, differential, interstage lowpass filter between the LTC5594’s mixer outputs and its IF amplifier inputs. At the IF amplifier outputs, a 1GHz bandwidth, differential, anti-alias lowpass filter is constructed using capacitors C17-C18, C20-C21, C23-C24, and inductors L5-L8. The values for resistors R3 and R4 are chosen to generate a nominal 1.35V output common-mode voltage for proper DC coupling to the AD9208 ADC inputs.
The standard AD9208 Evaluation board (AD9208-3000EBZ) is reconfigured for DC-coupled, differential input by removing the capacitors C179-C180 and resistors R112-R113, and replacing C103-104 and R110-111 with 0Ω jumpers. The ADC evaluation board inputs are then directly connected to the demodulator evaluation board’s outputs via 3-inch long, low loss, 50Ω, coaxial cables.
A DC590B Isolated USB Serial Controller and the QuikEval software are used to control and monitor the LTC5594 demodulator’s internal control registers via its SPI serial bus. An ADS7-V2EBZ FPGA Based Data Capture Kit and the Analysis | Control | Evaluation (ACE) Software are used to control the AD9208 ADC and to capture its output onto a computer. Laboratory RF signal sources are used to generate the test signals and appropriate LO and clock signals required for the demodulator, ADC, and FPGA. A block diagram of the actual measurement setup is shown in Figure 2. Figure 3 shows the ACE software configuration for the FPGA and ADC. A captured ADC digital output is shown in Figure 4.
Figure 2. Measurement Setup
Figure 3. Analysis | Control | Evaluation (ACE) Software
Figure 4. ADC Digital Output Captured in ADI Analysis | Control | Evaluation (ACE) Software
With LO being held constant at 4GHz, the RF input signal was swept from 3.3GHz to 4.7GHz, and the resulting IF output was measured and recorded. Figure 5 shows the measure output fundamental tone power versus IF frequency. The IF output response has about -1.8dB slope across the 1GHz complex bandwidth. It is the cumulative response of the external RF signal path and the internal RF circuit. The ADC’s internal finite impulse response (FIR) filter roll-off is also clearly visible. The prominent IF output ripple is due to the 3-inch interconnect cable and the transmission lines on the evaluation board PCBs. This demonstrates the importance of compact layout with minimum trace length.
Figure 5. Measured Fundamental Tone Power vs. IF Frequency
Using the QuikEval software GUI, shown in Figure 6., image rejection of the system was optimized at 200MHz by carefully tuning the LTC5594’s IQ phase and gain error adjust registers.
Figure 6. LTC5594 QuikEval Software GUI
Figure 7 shows image rejection versus IF output frequency after image rejection was optimized at 200MHz. The image rejection is better than 48dB across the 1GHz complex bandwidth.
Figure 7. Measured Image Rejection vs. IF Output Frequency
In this example, we demonstrate the evaluation of the LTC5594 demodulator with the AD9208 ADC using on their respective evaluation boards using common lab equipment. A more in-depth discussion of the interstage and anti-alias filter design will be presented in a later article.