Placing a 1 kO resistor on the control line of ADRF5730 would introduce a delay of less than 5 ns on the digital pins, which should not affect the part's operational characteristics, given the 250 ns 0.1 dB settling time. If the power-up sequence is not followed, placing a 1 kO resistor is recommended to ensure that the digital pin current remains below 3 mA. Limiting the output current from the FPGA output pin to less than 3 mA can also help prevent damage to the chip.