DEMO-AD5700D2Z HART_CLK connection

Question

Hi, 
 This is regarding DEMO-AD5700D2Z board. I just started programming and evaluate the performance of the ICs in-order to zero in on them. I see that HART_CLK is connected to both P2.0 and P1.0. Can someone please explain me what is the reason to connect to two pins? 
 Also, on a custom board, I want to connect HART_CLK to just P1.0 as I want to use P2.0 and P2.1 as I2C lines. Is it feasible? 
 Thanks, 
 Spoorthy 
 ad5700 ad5700-1 hart demo-ad5700d2z

ADIApproved · Accepted Answer

Hi Spoorthy, 
 To clarifiy the HART_CLK signal on P1.0 and P2.0. These can potentially be used as clock input to provide synchronization/calibration of the ADuCM360 timing by the AD5700 clock. 
 In the demo application, these were not used because the AD5700 crystal oscillator and the ADuCM360 internal clock were already accurate enough for the application. 
 P2.0 can be used as clock input for UART clock 
 P1.0 can ba an interrupt source for the Timer 0 and Timer 1 
 That is why the pins were connected. Hope this answers your question. 
 Thanks 
 JB)

FormerMember · Answer

Hi Spoorthy, 
 P2.2 is the only pin that can provide the UART download mode (as JB mentioned above), but you don't need P2.2 in order to use the I2C communications bus. 
 I2C is actually available on 2 sets of pins, P2.0/P2.1 and P0.1/P0.2. So if you need I2C communication you could use that other set of pins (P0.1/P0.2) and keep the connections to the HART_CLK as described in the CN0267 . 
 I'm not sure why the HART_CLK is connected to 2 sets of pins. If you look at the pin functions, one is used as a potential UART Clock input (P2.0) and the other is an External PWM synchronization pin or External clock source (P1.0). So perhaps in this application for the HART modem those functions are used in the software to do some application specific functions. 
 Cheers, 
 Brandon

ADIApproved · Answer

Hi Spoorthy, 
 On J-Link OB emulator, this is only included with ADuCM360 eval kit. You may look for other J-Link/Segger debuggers on the market. This will also be compatible when using the SWD lines. Just double check to make sure they have appropriate drivers available. 
 On the HART_CLK, I am still confirming the function of this with another engineer. I see this CLK_OUT signal from the HART modem is not used in certain applications. I still have to make sure if this has a specific function for this eval board. Depending on your design and software stack, there is a possibility that you may not need the HART_CLK signal. 
 I will get back to you if I can get the definite answer. 
 Thanks 
 JB

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DEMO-AD5700D2Z HART_CLK connection