DEMO-AD5700D2Z HART_CLK connection

Hi Brandon,

Thanks for the reply.

>P2.2 is the only pin that can provide the UART download mode (as JB mentioned above), but you don't need P2.2 >in order to use the I2C communications bus.

Yes, I realized this. Sorry, my bad.

>I2C is actually available on 2 sets of pins, P2.0/P2.1 and P0.1/P0.2.  So if you need I2C communication you could >use that other set of pins (P0.1/P0.2) and keep the connections to the HART_CLK as described in the CN0267

But I need to use P0.1 and P0.2 for external UART in order to download code and analyse. I cannot invest on the J-link debugger right now as I cannot buy it separately, but only with Evaluation board of ADuCM360. Could you please let me know if there's a way to buy just the J-Link OB Emulator?

>I'm not sure why the HART_CLK is connected to 2 sets of pins.  If you look at the pin functions, one is used as a >potential UART Clock input (P2.0) and the other is an External PWM synchronization pin or External clock source

>(P1.0).  So perhaps in this application for the HART modem those functions are used in the software to do some >application specific functions.

Could I configure P1.0 as potential UART clock input or do you foresee any problems by doing that?

Thanks,

Spoorthy

Hi Spoorthy,

On J-Link OB emulator, this is only included with ADuCM360 eval kit. You may look for other J-Link/Segger debuggers on the market. This will also be compatible when using the SWD lines. Just double check to make sure they have appropriate drivers available.

On the HART_CLK, I am still confirming the function of this with another engineer. I see this CLK_OUT signal from the HART modem is not used in certain applications. I still have to make sure if this has a specific function for this eval board. Depending on your design and software stack, there is a possibility that you may not need the HART_CLK signal.

I will get back to you if I can get the definite answer.

Thanks

JB

Hi JB.Chua,

Thanks for the update.

Will wait for your reply.

Regards,

Spoorthy

Hi Spoorthy,

To clarifiy the HART_CLK signal on P1.0 and P2.0. These can potentially be used as clock input to provide synchronization/calibration of the ADuCM360 timing by the AD5700 clock.

In the demo application, these were not used because the AD5700 crystal oscillator and the ADuCM360 internal clock were already accurate enough for the application.

P2.0 can be used as clock input for UART clock

P1.0 can ba an interrupt source for the Timer 0 and Timer 1

That is why the pins were connected. Hope this answers your question.

Thanks

JB

Hi JB,

Thanks for the clarification.

Could I configure P1.0 as clock input for UART clock, if required later in my application?

I'm new to HART and still not sure if I'll be requiring HART_CLK in my application or not.

Thanks,

Spoorthy

Hi Spoorthy,

Looking at the datasheet, only P2.0 pin can be used as the UART_CLK input.

If you need both I2C and UART for your application, and want to keep the option of the UART_CLK pin available in case your application needs it, I would suggest doing the following.

• Use P0.1 and P0.2 as the I2C bus (SDA and SCL)
• Use P0.6 and P0.7 as the UART Tx/Rx
• That would give you access to P2.0 for the UART_CLK pin if you need it later, and you could also synchronize using the P1.0 pin like shown on the Demo hardware.
• If you happen to need a SPI bus there is still the option of using P1.4, P1.5. P1.6 and P1.7 pins.

Cheers,

Brandon