Thread Details

  • State Verified Answer
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 44 subscribers
  • Views 278 views
  • Users 0 members are here
Options
 
Related Content

        

            Post
             Go back to editing
        

    

    


    

    









		


















	
	
			
	
			
		
	
	
		

	    
	    
	    		
CN0566 Pluto interconnection

		
	
				

			

									
					    m1nl
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Sep 18, 2025 
				
			
			
		
    
		
		                    	    
    
        	    
    Thread Summary
    
                The user is considering interfacing the CN0566 with an SDR solution other than the PlutoSDR and asks about SPI signal routing and 3.3V CMOS level tolerance. The final answer clarifies that the SPI interface is provided by the Raspberry Pi, not the PlutoSDR, and that level shifting is used between the Pi's 3.3V and the ADAR1000 and ADF4159's 1.8V levels. The 14-pin connection between the Pluto and CN0566 is only for TXData, and external level shifting is required for TXDATA_1V8 if the FPGA pin bank is not operating at 1.8V CMOS. The accompanying answer confirms that the PL GPIOs are routed to the EMIO GPIO peripheral in the HDL for proper signal handling.
                        	    
    
                
                     AI Generated Content
                
    	    
    
             
				
        		
    
		    
		    		    
    
		      		            		        
    Category: Datasheet/Specs
    
    		        		            		    
    Product Number:  CN0566 
    
    		        		    		    
    
		    		    
		    			
    
			    
    Hi,
    

    I’m considering interfacing the CN0566 with an SDR solution other than the PlutoSDR. I’ve reviewed the PlutoSDR HDL and schematic, and I believe I understand the GPIO connections required.
    

    I have two questions to better understand the design:
    

    1. While going through the CN0566 schematic, I noticed the SPI signals (SDIO, SDO, SCLK, CSB0, CSB1, CSB2) are not routed to the 14-pin socket. Could you clarify whether the PlutoSDR actually provides this SPI interface to the board? If so, is it implemented through the axi_quad_spi interface in the HDL? Additionally, how are the CSBx signals intended to be routed? I've attached part of the schematic I'm referring to.
    

    2. Is there any way to make the CN0566 board tolerant to 3.3 V CMOS levels when interfacing with an SDR device?
    

    

    Thanks in advance for your help.
    

    

     
    
			
    
			
									
		                             
                        

    
    
                                            
                 Datasheet/Specs
                
                                                    
                 plutosdr
                
                                                    
                 cn0566
                
                                
            
    
    
    
		
    

				
				        
        		
    
			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		
    

        
        
        
    
					
    
			
    


    
















    
	
    
	
    
					



			


				
	









	
      
	

    • 
	
      



	
			
		
	



      
	
      
		
      
							
					
      
		
      
		    
		    		    
			
				
									
							        
			
			
			
      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Sep 18, 2025 5:22 PM
            
            
						
			            		
      
		
										+1
					
	
      

		
		
      
		
      
                                
                                                            
      
					
      Hi  , the Pluto does not provide the SPI interface, the Raspberry Pi does. I believe the axi_quad_spi in the HDL is left over from an experiment during development.
      

      There's level shifting between the Pi's 3.3V levels and the ADAR1000 and ADF4159's 1.8V levels. This is on the same schematic sheet as the P1 screenshot you have.
      

      The 14-pin connection between the Pluto and CN0566 main board is only for the TXData signal, so the Pluto can tell the ADF4159 when to start ramping in FMCW examples. The subsequent data capture is synchronized to this signal.
      

      You would have to level shift the TXDATA_1V8 signal external to the board, it goes directly to the ADF4159. Ideally, power the level shifter from the VDD1V8 rail so there is no chance of driving a high level into the ADF4159 if power is not present.
      

      -Mark
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
						
						
				
				
		
		
      
			
		
      
	
      

      

      • 

	

    • 
	
      



	
		
	
	



      
	
      
		
      
							
					
      
		
      
		    
		    		    
			
				
									
							        
			
			
			
        
            
						
                            
            
            				
            
                on Sep 18, 2025 5:53 PM
            
            
												
						in reply to MarkThoren
					
										
			            		
        
		
										0
					
	
        

		
		
        
		
        
                                
                                                            
        
					
        Hi Mark,
        

        Thank you for the prompt response. axi_quad_spi is routed to the PL GPIOs, so I believe it is up to the user how to utilize this feature when the Pluto is not in Phaser mode. In Phaser mode, these PL GPIOs are routed to TDD instead, which would create a conflict if the PlutoSDR were to provide SPI interface.
        

        # PL GPIOs
        #
        # Pin  | Package Pin | GPIO     | Pluto    | Phaser  |
        # -----|-------------|----------|----------|---------|
        # L10P | K13         | PL_GPIO0 | SPI MOSI | TXDATA  |
        # L12N | M12         | PL_GPIO1 | SPI MISO | BURST   |
        # L24N | R10         | PL_GPIO2 | SPI CLKO | MUXOUT  |
        # L7N  | N14         | PL_GPIO3 | IIC SDA  | IIC SDA |
        # L9N  | M14         | PL_GPIO4 | IIC SCL  | IIC SCL |
        

        So to conclude:
        

        Based on the schematic, TXDATA (output), BURST (input), and MUXOUT (input) should be routed to the EMIO GPIO peripheral in the HDL, with proper level shifting applied whenever the FPGA pin bank is not operating in the 1.8 V CMOS standard.
        

        Mateusz
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

        • 

	

      • 
	
        



	
			
		
	



        
	
        
		
        
							
					
        
		
        
		    
		    		    
			
				
									
							        
			
			
			
        •  Analog Employees  
        
            
						
                            
            
            				
            
                on Sep 21, 2025 6:19 PM
            
            
												
						in reply to m1nl
					
										
			            		
        
		
										0
					
	
        

		
		
        
		
        
                                
                                                            
        
					
        Your understanding is correct. The SPI would not be used with the phaser, one possible use would be to control an ADF4159 eval board (with appropriate modifications).
        

        Note that I don't think we actually use MUXOUT, it serves several functions (hence the name), refer to the ADF4159 datasheet. Also BURST is for future use as well, it's a GPIO from the Raspberry Pi, which could be used as an input to the TDD as an alternative to software triggering, which is what is currently used.
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
						
						
				
				
		
		
        
			
		
        
	
        

        

        •