Hi Experts:
We design a FPGA motherboard for cn0511, and plan to generates a DC-5GHz RF signal. The configurations of AD9166 we want to adopt are:
-- 2*NRZ,
-- NCO mode only, DC_TEST_EN = 1,
-- Integer NCO Mode,
-- Main NCO Frequency Hopping,
-- DC TEST Data( 0x14E 0x14F) for amplitude adjustment, which means I_OUTFS is fixed.
The register map we initialized is as follew:
But we found a very strange problem. It seems to be OK with the signal frequency close to 6GHz/2^n(n = 1,2,...), but intermittent with the signal
frequency away from 6GHz/2^n(n = 1,2,...), e.g. OK for 750MHz, 1.5GHz, intermittent for 647MHz, 1.15GHz. The normal situation is as follows
The abnormal situation is shown below
So How can we fix this problem? Any help is appreciated, Thank you!
