CN0540 Example Program Ported to STM32 NUCLEO-L496ZG: Getting Started, FAULT

I did a 9  - Reset ADC,  1 - Soft reset - over SPI, and 5 - Set ADC to default config, and got ad77681 successfully initialized, Default ADC settings successfull. The FAULT light is still on. 

I tried 21 - Compenzate Piezo sensor offset and it appeared to hang, but when I pressed the RESET button it ran successfully! Now, 12 - Read ADC *CENSORED* status returns

== *CENSORED* STATUS REGISER
*CENSORED* error: OK
ADC error: OK
Dig error: OK
Ext. clock: OK
Filter saturated: OK
Filter not settled: OK
SPI error: OK
POR Flag: OK

However, the FAULT LED is still on!

I have taken some voltage measurements:

From the ADG5421F datasheet, "To activate the switches ... The input signal must be between VSS − VT and VDD + VT." I'm seeing 12.49V, which is between -0.7 and 26.7. Again from the ADG5421F datasheet, "The FF pin is an open-drain output that requires an external pull-up resistor. The output of the FF pin is high when both the Sx pins are within the normal operating range." Does that mean that the CN0540 FAULT light is normally on, and goes off to indicate a FAULT?

So, maybe I've got it running OK. Now to try to collect some data and take an FFT.

Hi CK3,

Yes, you got it right. 

The CN0540 Fault light is normally on since it has an open-drain output which requires pull-up resistor which cause the LED to be "ON" by default and the digital output pulls low when a fault condition occurs on either of the Sx inputs.

Regards,

Michelle

Great, thanks! I guess there is no relation between the FAULT light and faults reported by 12 - Read ADC [censored] status, correct? How can I clear all of the fault flags? For example, I have this condition:

12
== [censored] STATUS REGISER
[censored] error: FAULT
ADC error: OK
Dig error: OK
Ext. clock: OK
Filter saturated: OK
Filter not settled: OK
SPI error: OK
POR Flag: FAULT

As far as I can tell, the POR Flag is just telling be that a reset has occurred. Well, yeah, I did the reset to try to clear the flags. Does it hurt anything having these FAULT flags set? 

Hi CK3 

You’re right: when you perform reset, the POR flag bit will be set to 1. The POR flag indicates that a reset or a temporary supply brown out occurred.  When performing the “12 - Read ADC master status” command after reset, the POR Flag will indicate a fault. To clear this, just perform another “12 - Read ADC master status” command.

Just to add on your previous inquiries, the “Filter saturated: FAULT” indicates that the digital filter is clipped on either positive or negative ADC full scale. Check that differential voltage at the input of the ADC is within +/- 4.096V.

Regarding the “21 - Compenzate Piezo sensor offset”, it takes some time to perform this command (around ~30 seconds for each compensation iteration). I would avoid typing in other commands during this phase. See screenshot.

The only reason I could think of that will cause a true hang-up using this command is when the MCU did not receive the DRDY interrupt signal from the ADC, which is unlikely.

On another note, the DC offset / bias voltage that DAC can compensate is only up to 13V. DC offset / bias voltage greater than 13V may result to “Filter saturated: FAULT”. Check the voltage at P1 pin 2, this should be <13V. A successful “21 - Compenzate Piezo sensor offset” should have a final mean voltage close to 0V (i.e. “Final Mean Voltage: -0.000079”, see screenshot above)

Regards,
Malcolm

Thanks, Malcolm. I'm still struggling to capture some meaningful data.

malcolm_kwok said:

You’re right: when you perform reset, the POR flag bit will be set to 1. The POR flag indicates that a reset or a temporary supply brown out occurred.  When performing the “12 - Read ADC master status” command after reset, the POR Flag will indicate a fault. To clear this, just perform another “12 - Read ADC master status” command.

Ah, that works!

malcolm_kwok said:

Just to add on your previous inquiries, the “Filter saturated: FAULT” indicates that the digital filter is clipped on either positive or negative ADC full scale. Check that differential voltage at the input of the ADC is within +/- 4.096V.

Regarding the “21 - Compenzate Piezo sensor offset”,

I'm having difficulties here. Once I got it to zero out perfectly, as measured at R22 & R23; ADA4945-1 +IN & -IN. But most of the time, it winds up way out. 

malcolm_kwok said:

On another note, the DC offset / bias voltage that DAC can compensate is only up to 13V. DC offset / bias voltage greater than 13V may result to “Filter saturated: FAULT”. Check the voltage at P1 pin 2, this should be <13V. A successful “21 - Compenzate Piezo sensor offset” should have a final mean voltage close to 0V (i.e. “Final Mean Voltage: -0.000079”, see screenshot above)

I see 12.5 V even at P1 pin 2 with the Wilcoxon 786A connected. In the Circuit Note, there are several measurements taken with "shorted inputs". I'm thinking I should get that configuration working right and connect the IEPE sensor later. However, I have questions about what "shorted inputs" really means. Just a jumper on P1? Maybe move the jumper from P10 to P1? Why is "inputs" plural?

If I do move the jumper from P10 to P1 and run 21 - Compenzate Piezo sensor offset, I get this:

21
Initialize SAR loop (DAC MSB set to high)
DAC code:8000 Mean Voltage: 0.010298
UP

SAR loop #: 15
DAC code:c000 Mean Voltage: 0.000000
DOWN

SAR loop #: 14
DAC code:a000 Mean Voltage: 0.000000
DOWN

SAR loop #: 13
DAC code:9000 Mean Voltage: 0.050751
UP

SAR loop #: 12
DAC code:9800 Mean Voltage: 0.000000
DOWN

SAR loop #: 11
DAC code:9400 Mean Voltage: 0.048056
UP

SAR loop #: 10
DAC code:9600 Mean Voltage: 0.000000
DOWN

SAR loop #: 9
DAC code:9500 Mean Voltage: 0.047382
UP

SAR loop #: 8
DAC code:9580 Mean Voltage: 0.000000
DOWN

SAR loop #: 7
DAC code:9540 Mean Voltage: 0.000000
DOWN

SAR loop #: 6
DAC code:9520 Mean Voltage: 0.012682
UP

SAR loop #: 5
DAC code:9530 Mean Voltage: 0.070886
UP

SAR loop #: 4
DAC code:9538 Mean Voltage: 0.047236
UP

SAR loop #: 3
DAC code:953c Mean Voltage: 0.000000
DOWN

SAR loop #: 2
DAC code:953a Mean Voltage: 0.000000
DOWN

SAR loop #: 1
DAC code:9539 Mean Voltage: 0.012551

Final DAC code set to:0 Final Mean Voltage: 0.000000

Offset compenzation done!

Now, if I do 12 - Read ADC [censored] status, I get this:

12
== [censored] STATUS REGISER
[censored] error: FAULT
ADC error: OK
Dig error: OK
Ext. clock: OK
Filter saturated: FAULT
Filter not settled: OK
SPI error: OK
POR Flag: FAULT

P7, SHIFT, is 35.1 mV.

R22 (ADA4945-1 [FDA] +IN) is 1.81 V, R23 (-IN) is 1.39 V, difference is 0.424 V. 

R64 to R65 (FDA_OUT_N & FDA_OUT_P) is 4.96 V.

C9 (AD7768-1 AIN+ & AIN-) also measures 4.96 V; clearly outside the range of -4.096 - +4.096, which explains the Filter saturated: FAULT, right?

I am making some great progress. The breakthrough came when I realized that the SHUTDOWN signal is active low, which was not obvious to me until I studied the schematic. I had been running with the DAC buffer disabled!

malcolm_kwok said:

Regarding the “21 - Compenzate Piezo sensor offset”, it takes some time to perform this command (around ~30 seconds for each compensation iteration). I

You're not kidding. I thought I still had a hang, and was trying various things until I got distracted while it was running and came back a while later to find that it had run to completion!

As a sort of verification test, I connected a 1 kΩ resistor across P1 (GND and VIN) and did 17 - Do the FFT, which yielded:

THD:-2.038 dB
SNR:-7.394 dB
DR:104.990 dB
Fundamental:-117.300 dBFS
Fundamental:148.438 Hz
RMS noise:25.390626 uV
LSB noise:52.000

12 - Read ADC [censored] status reports no FAULTs. Then, I did 18 - FFT settings, 3 - Print FFT plot, and then graphed the results:

This seems to accord well with Figure 10. FFT for the DC-Coupled Solution with Shorted Input, DAC Output
at Half Scale in the Circuit Note.

Now, I think I'm ready to connect the Wilcoxon IEPE sensor.

I am making some great progress. The breakthrough came when I realized that the SHUTDOWN signal is active low, which was not obvious to me until I studied the schematic. I had been running with the DAC buffer disabled!

malcolm_kwok said:

Regarding the “21 - Compenzate Piezo sensor offset”, it takes some time to perform this command (around ~30 seconds for each compensation iteration). I

You're not kidding. I thought I still had a hang, and was trying various things until I got distracted while it was running and came back a while later to find that it had run to completion!

As a sort of verification test, I connected a 1 kΩ resistor across P1 (GND and VIN) and did 17 - Do the FFT, which yielded:

THD:-2.038 dB
SNR:-7.394 dB
DR:104.990 dB
Fundamental:-117.300 dBFS
Fundamental:148.438 Hz
RMS noise:25.390626 uV
LSB noise:52.000

12 - Read ADC [censored] status reports no FAULTs. Then, I did 18 - FFT settings, 3 - Print FFT plot, and then graphed the results:

This seems to accord well with Figure 10. FFT for the DC-Coupled Solution with Shorted Input, DAC Output
at Half Scale in the Circuit Note.

Now, I think I'm ready to connect the Wilcoxon IEPE sensor.

Hi CK3 

Great to hear that you were able to make the circuit work.
Having it in "shutdown" affects "DAC_BUF_EN" and "SW_IN" nodes, which affects a lot of sub-blocks in the circuit, including the ADA4807 amplifiers. A disabled amplifier can rail to either supply voltage, making it very unpredictable. 

To be clear, "shorted inputs" in this circuit means shorting the VINP input node to ground.
Like what you were saying, having a jumper across P1 would achieve this, ideally having VINP=0V.

I believe that 12.5V is the DC bias of the sensor, which can be compensated by the DAC. I hope you are able to get a sensible output from the accelerometer!

Regards,
Malcolm

malcolm_kwok said:

I believe that 12.5V is the DC bias of the sensor, which can be compensated by the DAC. 

With the sensor connected I see:

VIN (P1): 12.49 V

SHIFT (P7): 4.68 V

malcolm_kwok said:

I hope you are able to get a sensible output from the accelerometer!

It looks good so far. FFT with the 786A just lying on the bench:

THD: -1.475 dB
SNR: -1.380 dB
DR: 98.336 dB
Fundamental: -102.672 dBFS
Fundamental: 179.688 Hz
RMS noise: 83.984378 uV
LSB noise: 172.000

I (loosely) attached a vibrator and got this:

THD: -7.439 dB
SNR: -4.976 dB
DR: 51.531 dB
Fundamental: -56.702 dBFS
Fundamental: 1210.938 Hz
RMS noise: 9252.442047 uV
LSB noise: 18949.000

No FAULTs are reported in the [censored] Status Register.