Diverging from traditional LTspice models for DACs, focusing on the product’s output stage with simulations covering performance such as headroom, footroom or settling times, the LTspice model for the AD3552R revamps these models with a more digital simulation. The functionality of some registers in the model, in particular those related to digital gain scaling and DC offset, can now be simulated. The LTspice model is also able to reproduce dynamic and noise performance with high fidelity.
Figure 1, AD3552R DAC Channel Architecture Block Diagram
The AD3552R DAC offers unprecedented flexibility in the configuration of the voltage span while preserving full 16-bit accuracy, with a collection of 15330 unique output ranges with 16-bit resolution resulting from the combination of:
The theoretical formulae for the output stage of the DAC included in the LTspice model together with the electrical features of the DAC, allow for the simulation of static and dynamic behaviour using the very same values that are configured in the AD3552R’s internal registers.
Figure 2, AD3552R LTspice model
The parameters GAIN_SCALING_P, GAIN_SCALING_N, OFFSET_POLARITY and OFFSET take the same values as the corresponding fields in the register set of the DAC. Therefore, the configuration that is tested in LTspice can be easily translated to the SW. The digital code is modeled as an analog signal VDAC ranging from 0 to VREF, as it is done traditionally for other DAC models.
The same LTspice circuit can be used to adjust the output range, tune the step response, measure the effective bandwidth and evaluate the noise density for different codes. 
Figure 3. LTspice Circuit including the AD3552R Precision Digital-to-Analog Converter
The DC sweep simulation is useful to confirm the span of the output voltage for a given configuration of parameters. The limitations imposed by the operational amplifier in terms of headroom and footroom are also taken into account, so it is easy to anticipate any saturation of the output signal.
.dc V8 0 2.5 0.05
Figure 4. AD3552R Output Range
The transient simulation with a step waveform is useful to adjust the value of the feedback capacitor and the output filter of the TIA to achieve the desired rise time, settling time and overshoot. This simulation can be combined with a parametric sweep to find the optimal values of the parts. The value is a starting point because the simulation circuit does not include the parasitic effects of the board and the packages of the parts.
However the simulation takes into account the driving capability of the amplifier and DAC to estimate the slew rate and rise time of the signal.
.tran 0 10u 0 10n .step param Cf 3.5p 4.5p 0.2p
Figures 5 and 6. AD3552R Step Response Tuning combining a Transient Simulation with a Parametric Sweep
The AC Sweep simulation is useful to adjust the values of the feedback capacitor and the output filter of the TIA in applications where the output signal is harmonic.
.ac dec 30 1 100Meg
Figure 7. AD3552R AC Bandwidth
The Noise simulation is useful to predict the noise density expected at the output of the DAC and the TIA, both in the 1/f region and the thermal noise region. The LTspice model of the AD3552R captures the variation of noise density with the code. On the other hand, LTspice takes into account the gain of the TIA to scale up the noise at the output of the current DAC.
.noise V(Vout) V3 dec 10 1 100Meg .step param Vd list 0 1.25 2.5
Figure 8. AD3552R Noise Density
Check out the AD3552R LTspice model for a complete simulation and go to the AD3552R product page to learn more about this Multi-Span Output, Multi-IO SPI fast-DAC.
Simulation results can be checked against the EVAL-AD3552R Evaluation Board, already available for ordering.
To download LTspice software click on this link.
The Ibis model for the product is also available for reference on the AD3552R product page.
