Hi,
I keep seeing the term "Easy Drive" on newer SAR ADCs from Analog Devices.
What are the advantages of this new architecture and how does this help with signal chain design?
Thanks!
AD4020
Recommended for New Designs
The AD4020 is a high accuracy, high speed, low power, 20-bit, Easy Drive, precision successive approximation register (SAR) analog-to-digital converter...
Datasheet
AD4020 on Analog.com
AD7768-1
Recommended for New Designs
The AD7768-1 is a low power, high performance, Σ-Δ analog-to-digital converter (ADC), with a Σ-Δ modulator and digital
filter for precision conversion...
Datasheet
AD7768-1 on Analog.com
Hi,
I keep seeing the term "Easy Drive" on newer SAR ADCs from Analog Devices.
What are the advantages of this new architecture and how does this help with signal chain design?
Thanks!
Newer devices like the AD4020, AD7768-1, and AD4630-24 utilize a new input architecture that reduces both ADC non-linear input current and the charge redistribution voltage step typically observed at the input of a precision ADC. This new mode has the effect of improving system performance, especially when lower power or lower bandwidth amplifiers are used to directly drive the ADC input. This new architecture is referred to as High-Z mode, and this mode coupled with a long acquisition phase create the Easy Drive feature set.
Easy Drive allows ADCs to be driven directly with precision amplifiers or signal conditioning stage, thus eliminating the need in many cases for a dedicated high speed ADC driver stage (that is typical in SAR ADC based designs). High-Z mode is most advantageous when paired with signal of interest bandwidths below 100 kHz. With High-Z mode enabled, the cutoff frequency of the input RC filter (that helps remove more wideband noise coming from the upstream signal chain components) can be set lower than with traditional ADCs. It also allows for larger R in the RC filter, and hence broadens the choice of lower power/bandwidth precision amplifiers for DC type signals. For input frequencies above 100 kHz, along with multiplexed applications, a driver stage many still be needed to ensure settling to the necessary resolution within the acquisition phase of the ADC
For more info, I recommend reading the following analog dialogue articles:
Driving High Precision Analog-to-Digital Converters
Next-Generation SAR ADC Addresses Pain Points of Precision Data Acquisition Signal Chain Design