Learnings from the Lab Part 1: Designing a Low-Noise PCB for an ADC Capable of 1ppm Linearity

Learnings from the Lab Part 1: Designing a Low-Noise PCB for an ADC Capable of <1ppm Linearity

Introduction

The AD4630‑24 is a high‑performance 24‑bit, 2 MSPS SAR ADC capable of delivering intrinsic linearity better than 1 ppm, making it suitable for demanding precision‑measurement applications. Realizing this level of performance, however, requires far more than selecting the right ADC. The surrounding circuitry—driver stage, reference subsystem, power tree, grounding architecture, and PCB layout—determines whether the ADC’s full capability is preserved or degraded after integration.

To help customers access this performance in a repeatable and predictable manner, we undertook a comprehensive redesign of one of our existing AD4630‑24 evaluation boards. The goal was twofold:

1. Modernize the board architecture by incorporating improved power‑chain and reference options.
2. Enable deeper insight into how real‑world system decisions affect noise, SNR, linearity, and overall signal fidelity.

This article—the first of a three‑part series—covers the architectural improvements made to the evaluation board and explains the technical rationale behind each design decision. Subsequent parts will focus on measurement methodology and a detailed analysis of how different driver and grounding configurations affect noise performance.

The redesigned AD4630‑24 EVB includes:

• A 24‑bit, 2 MSPS SAR ADC with internal REFIN buffer, averaging filter up to 2¹⁶, and SNR performance around 105.7 dB. This ADC has internal capacitors which simplify the board layout and design.
• Two fully differential ADA4945-1 amplifier paths optimized for low distortion and wide‑bandwidth operation. A key specification is settling time with its ability to settle to 18-bit resolution within 100ns. The adjustable VCOM allows direct alignment with the signal chain’s input common mode point. The ADA4945-1 also implements output voltage clamps to effectively limit the differential and common-mode signal levels, thereby protecting circuitry following the ADA4945-1 from being overdriven
• Two single‑ended ADA4896-2 amplifier stages, arranged as pseudo‑differential drivers for flexible input configuration. The high bandwidth (230MHz) and slew of 120 V/µs ensures stable behaviour when driving the dynamic input of a SAR ADC. This amplifier also offers a noise density of 1 nV/√Hz at 100kHz offset.
• A VCOM amplifier that generates the required common‑mode offset for single‑ended modes.
• Support for multiple precision references and an alternative –3.3 V rails for front‑end amplifiers.

The block diagram below shows the complete signal chain: input → anti‑aliasing filter → amplifier stage (single‑ended or differential) → ADC → digital output. This modularity allows end‑users to compare the practical performance trade‑offs between drive architectures without needing a new PCB.

Power‑Tree Modernization and Noise Mitigation

One of the most impactful areas of improvement involved the power‑distribution network. In the new EVB revision, we:

• Removed unused components, reducing coupling paths and parasitics.
• Replaced aging DCDC and LDO options with newer alternatives recommended by ADI’s precision‑power group.
• Added an alternative negative LDO to improve flexibility and mitigate supply‑ripple sensitivity.
  These changes collectively reduced broadband noise contributions and improved rail stability feeding both the ADC and amplifier stages.
• Clean, low‑impedance supplies are particularly important in SAR‑ADC systems, where dynamic input switching currents can interact with the supply network and degrade both noise and linearity.

 Enhancements to Reference Generation and Common‑Mode Architecture

Given the AD4630‑24’s precision capabilities, the reference subsystem is critical. The redesign implemented:

• A dedicated low‑noise LDO to isolate the reference from the rest of the signal chain.
• Two selectable precision references:
  • ADR4550
  • LTC6655‑LN (ultra‑low noise)
• An improved VCOM amplifier path, producing a stable and low‑impedance 2.5 V common‑mode level for single‑ended operation.

This isolation strategy reduces susceptibility to digital noise or transient loading from the amplifier rails—both common pitfalls when striving for sub‑ppm linearity.

Input‑Driver Design and Amplifier Selection

Driving a 24‑bit SAR ADC is non‑trivial due to the transient input switching, strict settling requirements, and demanding noise/distortion constraints. The evaluation board includes two complementary amplifier choices to support different signal‑chain topologies.

ADA4945‑1: Fully Differential ADC Driver for Maximum Linearity

The ADA4945‑1 is a low‑noise, low‑distortion, fully differential amplifier specifically designed to interface with high‑resolution SAR ADC inputs. Key advantages include:

Low noise and distortion

• Input‑voltage noise: 1.8–2.0 nV/√Hz
• Harmonic distortion:
  • −133 dBc HD2 / −140 dBc HD3 at 1 kHz
  • −133 dBc / −116 dBc at 100 kHz
    This ensures that the driver does not dominate the overall noise budget.

Fast settling for high‑speed SAR conversion

• 100 ns settling to 18‑bit accuracy

Built‑in common‑mode control

The ADA4945‑1 includes an internal VOCM feedback loop, keeping the differential outputs precisely centered around the ADC’s required common‑mode voltage.

Differential symmetry and output balance

The common‑mode loop maintains output symmetry and suppresses even‑order distortion—critical for fully differential SAR systems.

Why it’s ideal for this EVB:
The ADA4945‑1 matches the AD4630‑24’s input requirements: low noise, low distortion, fast recovery, and precise differential common‑mode alignment.

ADA4896-2: High‑Speed, Low‑Noise VFA for Single‑Ended Flexibility

The ADA4896-2 supports scenarios where customers need to evaluate single‑ended or pseudo‑differential sources.

Low wideband and 1/f noise

• 1 nV/√Hz wideband noise
• 2.4 nV/√Hz at 10 Hz

High bandwidth and slew rate

• 230 MHz bandwidth (G= +1)
• 120 V/µs slew rate
• 45 ns settling to 0.1%

Low distortion and rail‑to‑rail outputs

• −115 dBc distortion at 100 kHz (2 Vpp)
• Rail‑to‑rail output allows better utilization of the ADC’s input range.

Best fit for flexible or single‑ended systems

The ADA4896-2 is ideal where:

• the signal source is inherently single‑ended,
• lower power is desirable,
• the user needs a compact, high‑bandwidth interface.

Why it’s included on the EVB:
It gives customers the ability to evaluate single‑ended vs. differential topologies on one platform, demonstrating how amplifier architecture influences signal‑chain design for high‑resolution SAR ADCs.

Small but impactful changes were made to the amplifier input network: added capacitors increased the anti‑aliasing filter order, and optional resistors enabled footprint‑compatible amplifier substitutions. These updates allow the board to support both the high‑performance ADA4945 FDA path and the more configuration‑sensitive ADA4896 single‑ended path.

Conclusion:

The ADC‑side circuitry remained unchanged, but the surrounding system—power, reference, grounding, and drive chain—saw significant improvements. The final design removes earlier limitations, fixes known bugs, and provides the flexibility needed to study single‑ended vs. differential performance.

Future iterations may incorporate next‑generation references such as the ADR1001 and expand toward application‑specific boards for DAQ and DMM systems.