Overview:

The ADP1046A offers flexibility when designing the PWM timing for many topologies. This app note focuses on the Phase Shifted Full Bridge topology, where Zero Voltage Switching is required. It walks through the theory, and the design process using ADP1046A, highlighting important considerations along the way.

Background:

Power Supply designers focus heavily on efficiency of the systems they develop. One technique which is popular is to use Zero-Voltage-Switching (ZVS). ZVS is used in many power supply converter topologies. It uses the transformer leakage inductance to discharge the MOSFET output capacitance to zero volts before turning them on. This can significantly reduce turn-on switching losses, and hence improve the efficiency of the converter. This is especially true in high input voltage PSUs, such as server PSUs, where the MOSFETs typically operate with 400V or higher.

ZVS explained:

A Full Bridge topology consists of 4 switches, 2 sets of 2 series switches. The series switches are never both on at the same time, as the input would then be shorted directly to ground, resulting in shoot-through. But it is also not optimal to leave them both off for too long, as there will be body diode conduction, and therefore, losses. The best performance comes by only having them off for just as long as needed to avoid shoot-through. This time, when both series switches are off, is called the dead-time.

To explain ZVS, it is valuable to look at the MOSFET switch in terms of 3 components, that is a switch, body diode and output capacitance. Figure 1 shows a full bridge topology from this viewpoint.

Figure 1. Full Bridge Topology.

When QA and QD switches are both on, the source of QA is 400V (VIN+) and the drain of QD is connected to 0V (VIN-). QD’s output capacitor (CapD) is discharged. Since QC is off, QC’s output capacitor (CapC) is charged to 400V.

When QD is turned off, the primary current continues to flow, thanks to the leakage inductance of the main transformer. This causes the output capacitance of QD to be charged up from 0V to 400V. At the same time, CapC is being discharged from a potential of 400V to 0V.

The source of QA remains at 400V (VIN+) and the drain of QD moves to this voltage also. The speed at which it reaches 400V depends on the amount of energy stored in the main transformer when QD is turned off, the leakage inductance of the main transformer, and the output capacitance of the QD switch.

The drain of QC is always connected to 400V. And it’s source is connected to the drain of QD. Therefore, when the drain of QD reaches 400V, then there is 0V differential between QC’s source and drain. Turning on QC at this point means that there will be no energy loss in discharging it’s cap, CapC. This is Zero-Voltage Switching (ZVS), and is the way to minimize the switching losses in the power supply. The ADP1046A can be used to realize ZVS operation, and therefore, optimal efficiency performance from a switching loss perspective.

Figure 2: OUTD achieving ZVS. The VDS voltage has been reduced to 0V before the VGS has been turned on.

ZVS using ADP1046A; Basic setup:

A Phase Shift Full Bridge ZVS topology which incorporates synchronous rectification requires 6 PWM signals to control the 6 MOSFETs. 4 PWMs (OUTA, OUTB, OUTC, OUTD) are used for the primary side switches. 2 PWMs (SR1, SR2) are used to control the synchronous rectifiers on the secondary side of the isolation barrier. See Figure 1 for a typical Full Bridge Phase Shift topology schematic. The first thing required is to decide which PWM outputs of the ADP1046A are going to control which of the switches. Figure 2 shows the recommended setup. The reason for this is explained below.

 

Figure 3. ADP1046A Recommened initial PWM settings.

• OUTA and OUTB should be chosen as complementary inputs. These are the non-modulating PWM signals.  These are the lagging leg of the Full Bridge.
• OUTC and OUTD should be chosen as complementary inputs. These are the phase shifted PWM signals. These are the leading leg of the Full Bridge.
• OUTA and OUTD should be chosen as diagonal pair.
• OUTB and OUTC should be chosen as a diagonal pair.

   

Figure 4. Recommended MOSFET naming.

The ADP1046A allows dead-time to be set on each PWM output. This allows the designer great flexibility. As explained in the theory section, the ZVS timing is a function of the MOSFET and transformer components. This means that the dead-time required for ZVS operation will vary from design to design. The ADP1046A programmability allows this to be optimized for each design. It is recommended to begin ZVS evaluation with a lot of extra dead-time between falling and rising edges. This is to prevent shoot-through, and damage of the MOSFET components. For example, 250nsecs should be sufficient as a starting point. ZVS operation cannot be achieved over the full load range, so the user needs to decide a load current above which ZVS operation will be required. Turn on the Power Supply, and monitor the primary side transformer voltage waveform. This is shown in yellow in Figure 5.

Figure 5. Transformer primary side winding voltage waveform.

The falling edge marked by * is the primary side voltage when OUTA and OUTD are both turned on.
The falling edge marked by ** is the primary side voltage when OUTB and OUTC are both turned on.

Zoom in on *.

The following scope shots show the slew rate of the * edge for different load currents. The larger the load current, the faster the slew rate. This is because the inductor has more energy to discharge the voltage which is present on the MOSFET output capacitance.

Figure 6. Light Load Current Slew Rate. The MOSFET capacitance discharge time is approx 135nsecs.

Figure 7. High Load Current Slew Rate. The MOSFET capacitance discharge time is approx 70nsecs.

From the results measured above, the deadtime between complementary PWMs should be set to 70nsecs minimum. Anything longer than this will introduce body diode conduction losses. So, for OUTA and OUTB, the deadtime is set to 120nsecs. This includes guardbanding. For OUTC and OUTD, an extra 80nsecs needs to be added to this because of the extra amount that the VSBalance if it is needed. Therefore, 200nsecs is set as the deadtime for these edges.

Figure 8. Simulation results showing ZVS of leading leg and falling leg of full bridge.

Synchronous Rectifiers

In the ADP1046A, SR1 and SR2 control the synchronous rectifier circuit, the recommended setup of SR1 and SR2 are:

• SR1 rising edge: This is set to align with OUTC falling edge with a dead time.
• SR1 falling edge: This is set to align with OUTB rising edge with a dead time.
• SR2 rising edge: This is set to align with OUTD falling edge with a dead time.
• SR2 falling edge: This is set to align with OUTA rising edge with a dead time.

Figure 9. Recommended setup for synchronous rectifiers. SR1 rising edge is close to OUTC falling edge. SR2 rising edge is close to OUTD falling edge.

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