The output voltage of the reset line does not go to zero until the supply
voltage is approx 1V. This behaviour is not described on the ADM1816 datasheet?
This is a normal behavior for ADM1816, In fact most of the voltage supervisory
part would behave in a similar way. This is why we have the VCC spec form 1V.
Basically our part cannot control (drive the logic) when it is under voltage.
We guarantee the output logic when VCC is above 1V. Some of our competitor
don’t have this and that can be a bigger issue.
The idea here is 1V on RESET would not bring processor out of reset so the
system should behave at power up.