Q
We are running a simulation of the ADP5050 with Simplis to generate +3V3 withCH4. We have added more capacitors representative of the real application
(4x100uF + 1x22uF + 6x10uF + 8x4.7uF + 12x1uF + 4x470nF + 45x100nF + 17x47nF +
26x10nF). The point is that during the start up the controller seems to limit
the maximum current and voltage drops.
Is this a problem with the simulation model or is there a limit in the total
capacitance that can be connected at the output of the channel?
A
The simulator behaves like the chip, however there are some considerations :1. You MUST derate the ceramic capacitors for voltage. 4x100 uF does NOT equal
400 uF. All the ceramic capacitor companies have online tool to figure this out.
2. If you are looking at channel 1 or 2 you can change the current limit using
the gate resistor. In the simulation however, you have to change the current
limit by double clicking on the IC and changing the "SW Current Limit". Set it
to 6.44.
3. If you are interested in startup, make sure you output the STARTUP
simulation from the tool. This will configure things appropriately. In order to
correctly simulate you must start with the input voltage below the UVLO of the
IC and look at the transient simulation. You may be looking at the POP
simulation (periodic operating point), but things are simulated differently in
the POP. The soft start is skipped in POP so that it finds the periodic
operating point as fast as possible since that simulation is used for finding
the bode plot and doing compensation, NOT startup.
4. Be aware of how the load is applied. The tool applies a resistor equaling
full load at full output voltage. This may not be realistic. Less load will
allow more output capacitance before current limit.
5. Ultimately the chip will hit a maximum output capacitance that the chip
cannot start into at full load (see #4) however I don't think that you are
anywhere near that yet.
