Question The configuration is the following : 47pF (+-5%) connected between OSC_IN andground. Regarding the real Timeout Period , the Datasheet mentions 400ms typical value(400 ms × C/47 pF) The measurements show values from 250ms to 360ms. Never more than 400ms. Is there any known drift for the timeout period of the ADM696 when usingprecision external capacitor ? Answer Check the VCC level. The internal oscillator frequency of this part is known tohave a strong correlation with VCC. See these:https://ez.analog.com/message/122974?commentID=122974#comment-122974https://ez.analog.com/message/222195?commentID=222195#comment-222195

ADM696: Datasheet reset assertion guarantee

Question In the datasheet there is a contradiction: In the first page, the penultimate sentence reads "RESET assertion is guaranteed with VCC as low as 1 V." - On the following page though, in the table ADM696/ADM697?SPECIFICATIONS, VCC Operating Voltage Range is from 3.0 V to 5.5, and there is NO mention to the statement "RESET assertion is guaranteed with VCC as low as 1 V." Please let me know which one is true? Answer The device will be held in reset all the way down to 1V. The 3.0V to 5.5V spec refers to the normal operating range of the device (ie) where the monitoring circuit is functioning accurately, where the timeouts on the device work correctly. Once you drop below the 3.0V value, there is no guarantee that these circuits are working correctly. However, when Vcc is at this level you should be in reset anyway and the part is guaranteed to actively pull reset low all the way down to Vcc = 1V.

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ADM696 Production
The ADM696 / ADM697 supervisory circuits offer complete single chip solutions for power supply monitoring and battery control functions in microprocessor...
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ADM696 on Analog.com