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Subject: LTC2909IDDB-2.5#TRMPBF Reset_N is getting asserted even though Threshold Voltages @ J1 and J2 is Proper.

Category: Hardware
Product Number: Subject: LTC2909IDDB-2.5#TRMPBF Reset_N is getting assereted even though Threshold Voltages @ J1 and J2 is Proper.

Hi,

We are facing an issue with +15V Monitoring Circuit.


According to the resistor divider calculation voltage at J1 and J2 will be 534mV and 469mV.

1. We powered on the board, and the Voltage at J1 and J2 is  1.3 and 1.1 V.

  

2. Removing the IC, the voltage at J1 and J2 is measured to be 534mV and 469mV, as expected.

   The Net 15V_P_MON_OUT has not been connected anywhere. It is "Open" i.e High Impedance.

3. We Replaced the IC, still the voltage at J1 and J2 is measured to be 1.3V and 1.1V and the Voltage at RST_N (pin 5)  is 0.4v (i.e Reset_N is getting asserted).

4. We changed R3 resistor to 15K ohm such that the voltage at J1 is around 0.6V and J2 is 0.4V.

Still, the voltage at RST_N (pin 5)  is 0.4V.

5. We replaced R1, R2, and R3 with 1M ohm, 40K ohm, and 0 Ohm. (We intend to monitor only UNDER Voltage. It is mentioned in the datasheet to ground ADJ2 pin  if unused)

  We found voltage at J1 is around 1v. Still, the RST_N is asserted with a voltage of 0.4v.

We are monitoring -15V and 28v as well. The same kind of issue is present (Voltage at ADJ pin is meeting threshold but reset is asserted)

Please help us Debug this issue.

Regards,

UR Nikhil Bhat



We are monitoring -15V and 28v as well. The same kind of issue is present (Voltage at ADJ pin is meeting threshold but reset is asserted)
[edited by: Nikhil26 at 12:16 PM (GMT -4) on 14 Apr 2023]
Parents
  • Hi  ,

    Apologies for missing this question. For future questions regarding voltage supervisors, please post them on the Supervisory Circuits Sub-Group of Power Management so that we can answer your question in a timely manner.

    I will be looking into this, and will get back to you as soon as I have an update. Thanks.

    Regards,
    Karlo


  • Hi  ,

    I have checked this, and even tried to simulate your setup. The device should work and the /RST output should be de-asserted when there is a valid VMon (using your external resistive divider) and VCC. 

    Are you using a custom board? Would it be possible to test the device on a separate board with only the supply voltages? The ADJx pins of the device should not affect the external resistive divider voltages (they should remain at or very close to 534mV and 469mV even when the IC is connected). Could you also double check the orientation of the IC?

    Regards,
    Karlo

  • Hi,

    Are you using a custom board?    :   YES

    Would it be possible to test the device on a separate board with only the supply voltages?                                                                                                                                   :   YES, We did the setup on a perf board.  /RST output is being asserted.

    The ADJx pins of the device should not affect the external resistive divider voltages (they should remain at or very close to 534mV and 469mV even when the IC is connected).                                                                                                                                                                                                                                                            :   The voltages at the external resistive divider before and after mounting IC is different (1.3V and 1.1V as mentioned in the reply above)

    So We performed a little experiment:

    When VCC_ANG_15V_P is present, we have observed 1.3V at J1 & 1.2V at J2.
     
    When VCC_ANG_15V_P is not present, we have observed the same( 1.3V at J1 & 1.2V at J2.).

Reply
  • Hi,

    Are you using a custom board?    :   YES

    Would it be possible to test the device on a separate board with only the supply voltages?                                                                                                                                   :   YES, We did the setup on a perf board.  /RST output is being asserted.

    The ADJx pins of the device should not affect the external resistive divider voltages (they should remain at or very close to 534mV and 469mV even when the IC is connected).                                                                                                                                                                                                                                                            :   The voltages at the external resistive divider before and after mounting IC is different (1.3V and 1.1V as mentioned in the reply above)

    So We performed a little experiment:

    When VCC_ANG_15V_P is present, we have observed 1.3V at J1 & 1.2V at J2.
     
    When VCC_ANG_15V_P is not present, we have observed the same( 1.3V at J1 & 1.2V at J2.).

Children
  • Hi  ,

    Could you also double check the pinout of the device to your connections? 

    It is possible that the SEL is interchanged with ADJ1, TMR with ADJ2, VCC with REF, and GND with /RST. I have done this in simulation, and what comes out of SEL and TMR (thought of as ADJ1 and ADJ2) is around 1.36V and 1.2V respectively. If this is the case, then GND (thought of as /RST) won't ever de-activate as it is the GND.

    Regards,
    Karlo