I designed the same circuit as one described in figure 1 of the datasheet.(cascaded and supply exteded)
In my circuit, E1,2,3,4 in the master is assigned to the time position 2,3,4,5 ,respectively and E1,2 in the slave is assigned to the time position 6,7.
But, E1,2 sometimes rise in time position 6,7 and sometimes in 7,8.
So, I'm alillte confused now.
would you teach me the following questions to understand what is wrong in my circuit?
1. what is the CAS network looks like , who controlls and how is it controlled in each time position to pulldown ,keep low
2. do master and slave ahve own counter to reconginze the time position they are in now?
3. If the voltage at ON terminal of the slave exceeds 1V threshold tSTMR later than the voltage at ON terminal of the
master, does the conter value in slave is smaller(-1) than that in master?
because ON ternimal voltage in the slave exceeds after the falling edge on time position 1.