im looking for a pfc for a new application
input voltage: 380Vac to 440Vac 50Hz.
output voltage: 700V. 750V is possible too.
output power 2KW.
switching freq: 200Khz.
we dont want to use interleave solution.
the main demand is PF>0.99 and THD<3%.
can the ADP1047 meed those damands?
can you provide the eval board or similar app THD and PF spread sheet results from 20%Load to 100%Load?
Thanks,
Dudu Dayan
LT Gurur: I am told by local ADI foolks to post my multiple questions here.
Pl see at he whole list.
It would very much appreciated if you can shed some light on each issue.
Analog Devices ADP1047W Application Discussion
Questions/ Discussions on ADP1047W
In one of the items I submitted on the ADP1047 program availability is to have the ability to change the fixed delay on fast loop after a transient
In our system, RADAR operate ONLY in pulse load mode. I think our power stage will settle fast. Do you think it will be possible to change the fixed delay from 630ms to whatever we find suitable in 3 ph conditions?
More on current sense:
I am about to do our own power stage pcb while waiting for the Eval kit where I will learn how to use the GUI & check baseline waveforms.
Interestingly & fortunately, the current sense ADP1047 uses, copied below: is the same as in LT1248 or similar.
It is negative in the LT system.
It requires a whole lotta glue circuit to make it negative in a bridgeless PFC.
I would like to avoid having to use them because ADC with internal level shift capability can do miracles.
Below the sch, see what LT sees as this current to be & what our power stage can feed raw signal as detected in a utterly simple manner
LT1248 current brom bridge return node
Our power stage current waveform/envelope- it is “full wave” rectified with very high precision circuit)…but + side is not entirely gone.
A lot of effort to take out the positive side was spent, but I simply could not eliminate it by analog means without serious distortion.
Note that each ON time current are about the same: top trace is gate drive generated by LT1248, lower one is the current through the switch( linear segment only). Of ocurse, we can scale it down a lot more…but this gives you an idea about the waveform.
So the major question is: what should be done to keep the sensed current within the range useful to the ADP1047 controller?
We may have to start a conversation with the algorithm writers to figure out what to do.
I suspect one consequence of having the + side is that LT1248 does not converge & the output keep increasing indefinitely.
Any help will be highly appreciated.
Finally:
Hope you had perfect fireworks.
We did!
As we are nearing real work on the eval kit, one thing needs to be addressed.
As you have seen, the open loop line current of this power stage is of high fidelity.
But I have failed to see simulated version anywhere near it in closed loop.
Most likely culprit is current sensing scheme in LT129 or LT 1509
I synthesize the current through RS( .2 Ohm) – and it just is not what the model looks for.
In the ADP1047 I am hoping to explore more closely what exactly the algorithm processes.
If we cannot get same fidelity as open loop, we may have to use CS only for OC/ or similar functions.
Can we discuss this in depth & settle for one scheme asap?
I need to get my power board schematic done & out to the PCB designer.
Thnx
Robin
LT Gurur: I am told by local ADI foolks to post my multiple questions here.
Pl see at he whole list.
It would very much appreciated if you can shed some light on each issue.
Analog Devices ADP1047W Application Discussion
Questions/ Discussions on ADP1047W
In one of the items I submitted on the ADP1047 program availability is to have the ability to change the fixed delay on fast loop after a transient
In our system, RADAR operate ONLY in pulse load mode. I think our power stage will settle fast. Do you think it will be possible to change the fixed delay from 630ms to whatever we find suitable in 3 ph conditions?
More on current sense:
I am about to do our own power stage pcb while waiting for the Eval kit where I will learn how to use the GUI & check baseline waveforms.
Interestingly & fortunately, the current sense ADP1047 uses, copied below: is the same as in LT1248 or similar.
It is negative in the LT system.
It requires a whole lotta glue circuit to make it negative in a bridgeless PFC.
I would like to avoid having to use them because ADC with internal level shift capability can do miracles.
Below the sch, see what LT sees as this current to be & what our power stage can feed raw signal as detected in a utterly simple manner
LT1248 current brom bridge return node
Our power stage current waveform/envelope- it is “full wave” rectified with very high precision circuit)…but + side is not entirely gone.
A lot of effort to take out the positive side was spent, but I simply could not eliminate it by analog means without serious distortion.
Note that each ON time current are about the same: top trace is gate drive generated by LT1248, lower one is the current through the switch( linear segment only). Of ocurse, we can scale it down a lot more…but this gives you an idea about the waveform.
So the major question is: what should be done to keep the sensed current within the range useful to the ADP1047 controller?
We may have to start a conversation with the algorithm writers to figure out what to do.
I suspect one consequence of having the + side is that LT1248 does not converge & the output keep increasing indefinitely.
Any help will be highly appreciated.
Finally:
Hope you had perfect fireworks.
We did!
As we are nearing real work on the eval kit, one thing needs to be addressed.
As you have seen, the open loop line current of this power stage is of high fidelity.
But I have failed to see simulated version anywhere near it in closed loop.
Most likely culprit is current sensing scheme in LT129 or LT 1509
I synthesize the current through RS( .2 Ohm) – and it just is not what the model looks for.
In the ADP1047 I am hoping to explore more closely what exactly the algorithm processes.
If we cannot get same fidelity as open loop, we may have to use CS only for OC/ or similar functions.
Can we discuss this in depth & settle for one scheme asap?
I need to get my power board schematic done & out to the PCB designer.
Thnx
Robin
