The LT1372 data sheet claims that the S/S pin is "logic level compatible." But what exactly does this mean? I am driving the S/S pin with a 768 kHz square wave from an FPGA at 3.3 V and it's not switching. Pin 8, VSW is not toggling, it remains at the VIN level.
The circuit is basically the dual-output flyback converter shown in the data sheet.
With the S/S pin floating, the output switches as expected.