Category: Hardware
Product Number: LT8650S
Dear ADI team,
I’m pre‑designing with LT8650S and see a mismatch between LTpowerCAD v2.0 and LTspice 26.0.0:
Design
- VIN: 3.3 V (±100 mV), VOUT: 1.0 V, IOUT: 8 A (two channels paralleled, each with its own inductor)
- fSW: 1 MHz, FCM (SYNC floating)
- Inductors: 1.1 µH, DCR ≈ 3.47 mΩ
- Compensation: external RC//CC at VC + phase‑lead (CPL) at FB (paralleled pins VC/FB/SS per datasheet)
Observation
- LTpowerCAD shows ~59° phase margin and clean behavior.
- LTspice: from start to ~5 ms, VOUT = 1.0 V with ~170 µVpp ripple; after ~5 ms, average VOUT stays at 1.0 V but ripple jumps to ~50 mVpp.
Questions
- BIAS pin at low VOUT: datasheet says BIAS feeds the internal LDO only if BIAS > 3.1 V (tie BIAS to VOUT when VOUT ≥ 3.3 V). In my 1.0 V design, is BIAS = 1 V a bad choice for FCM stability? Should I tie BIAS to 3.3 V (with 1 µF local bypass)?
- Two‑phase 1 V/8 A @ 1 MHz: any recommended starting values for RC/CC/CPL to keep ripple < 10 mVpp, as advertised? (Typical ripple spec in datasheet.)
- LTspice setup: any known model nuances or simulation options (RELTOL/ABSTOL, startup directives, time‑step, etc.) for LT8650S paralleled in FCM at 1 V, 8 A, 1 MHz?
I can share schematic/waveforms from LTspice and the LTpowerCAD project if helpful.
Thanks,
Reinaldo González Reyes
