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LTC4151 Not ACKing Read Address

Thread Summary

The user encountered an issue where the LTC4151IMS#TRPBF NACKs the read address (0xCD) after a successful write transaction. The problem was resolved by using the correct individual device address (0xD4 for write, 0xD5 for read) instead of the mass write address (0xCC).
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Category: Hardware
Product Number: LTC4151

Using an LTC4151IMS#TRPBF.

I'm attempting to read the SENSE, VIN, and ADIN registers from a microcontroller over I2C @ 100KHz and coming across a very strange problem I haven't seen with this part before.

We are leaving both ADR pins open, so I've got an address of 0xCC for writing and 0xCD for reading.

I send the Write Address (0xCC) to begin and get an ACK from the part.  I then send the register I want to read and get another ACK from the part.  I then send the Repeated Start (Sr) condition followed by the address with the read flag (0xCD) and get no longer get an ACK from the LTC4151.  I get the same result for any of the registers I attempt to read (SENSE, VIN, ADIN).

Logic Analyzer capture of the transaction is below:

We've used this part before without any real issues, so I'm a little bit baffled on what could be going on here.  The chip itself is obviously active since it responds to its (write) address, I just can't figure why it would NACK the read address?  I did find another thread with a similar problem (here) but the solution doesn't seem to apply here, at least I don't think it does?  I'm sending all the clocks I should be sending (although after receiving the NACK from the target, my firmware doesn't attempt to continue reading and aborts the transaction by sending a STOP.  This is by design in the firmware).

As far as I can determine I am following the datasheet Fig. 7:

Any thoughts would be appreciated,

Thanks!

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