Design Review

Hi mhshawky ,

Thank you for sharing the schematic and test results. One concern is the limited headroom: 60 V input and 55.9 V output corresponds to about 93% duty cycle, placing the LTC7103 close to dropout.

See note 9 of the data sheet:

For VOUT above 43 V, the LTC7103 must use the datasheet’s high-output-voltage operating method, including the minimum VIN requirement:

VIN(MIN) ≥ VOUT / (1 − fSW × 260 ns)

At 300 kHz, a 55.9 V output requires approximately 60.6 V minimum input, so a 60 V rail does not provide adequate margin. Operation in this region may allow negative inductor current to accumulate during boost-capacitor refresh and could overstress the internal switches.

Please also confirm that EXTVCC is not connected to the 55.9 V output, since its absolute maximum rating is 41 V, and verify the failed board’s VIN-to-GND, SW-to-GND, and VOUT-to-GND resistances with power removed.

I recommend increasing input headroom or lowering the output voltage, then programming RUN/UVLO to prevent operation below the calculated minimum VIN.

Best,
Douglas

Hi mhshawky ,

Thanks for the update those changes look like good progress. Here's a quick confirmation of each item:

Operating point (62 V in / 55.6 V out, 200 kHz): Confirmed good. Duty cycle is ~89.7%, and your V_IN(MIN) math is correct: 55.6 / (1 − 200k × 260 ns) = 58.65 V, giving ~3.35 V of headroom from 62 V. That keeps you out of the near-dropout region.

EXTVCC open / internal LDO: Correct approach for a 55.6 V output. EXTVCC bootstrapping is only valid for V_OUT between 3.3 V and 40 V (abs max 41 V), so using the internal LDO is the right call here.

One item to adjust... UVLO threshold: You set UVLO rising to ~58.2 V, but your required V_IN(MIN) is 58.65 V, so the current setting is about 0.45 V too low. Since the RUN-pin divider is what actually enforces the minimum input, a UVLO below V_IN(MIN) still permits start-up/switching in the 58.2–58.65 V window the exact region we want to avoid for the dropout region we encoutered above.

I'd recommend raising UVLO rising to comfortably above 58.65 V... something like 59.5–60 V gives real margin while still allowing operation from your 62 V rail. Also confirm the UVLO falling threshold stays above 58.65 V; the RUN pin has ~100 mV hysteresis (1.21 V typ rising threshold), so account for that in the divider so it doesn't ride down into the dropout zone during a transient sag.

I Got this from the datasheet's Pin Functions (RUN, Pin 3) notes where it mentions a resistor divider is used between V_IN and RUN to function as an undervoltage lockout, and the Electrical Characteristics table gives the 1.21 V typ ON threshold with 100 mV hysteresis.

Once UVLO is nudged above V_IN(MIN), everything should be clear of the failure mechanism. Happy to help work out the exact divider values if useful.

Best,
Doug