blanking period

adding comments

I went back and simulated the entire stack in LT SPICE and i was able to replicate the problem. 

(Problem statement: after the initial firing of the MOSFET the chip turns off the MOSFET prematurely.)

My interpretation: When the primary conduction cycle ends and the drain voltage (on the secondary MOSFET) is pushed below ground the body diode starts conduction. The current in the MOSFET starts rising aggressively. The LT8309 triggers as the drain falls below its programmed threshold, and imposes a short delay after which it fires the MOSFET gate. The main n-channel of the MOSFET takes over conduction and the body diode shuts down after some delay. This transition can be seen as ripples on the drain of the MOSFET.  As the current rises in the MOSFET, its Ron forces the below ground voltage to further drop and things stabilize.

The critical time IMHO is the hand off between the body diode and the main channel. ( there is the issue of reverse recovery current of this diode, plus the capacitive parasitics of the MOSFET, plus resonances associated with transformer inductors - We have not in detail modeled this entire hand over process - but to my knowledge it is rather complex.  Once this very short transient period (<600ns) is over and the current through the MOSFETs n-channel has reached its peak the negative voltage in the drain grows linearly until it reaches the programmed threshold. 

comment: As indicated earlier, I am not sure why the chip's law was designed with such a short blanking period since the target frequency is around 100-140KHz. (I guess to appeal to ultra low load DCM operations). 

comment2: we recently designed a 1KW resonant LLC system and it appears the issue of controlling the secondary MOSFETs perfectly is a rather difficult enterprise. obviously at 1kW event driven cycle control is no longer valid.

The above led to the investigation of timing, of thresholds, and Ron of the MOSFET.  I resimulated the stack using a similar class MOSFET but higher Ron. (SPICE L0) Moved Ron from 7.5mOhm to 14mOhm, 20mOhm and 24mOhm respectively. The simulation showed that the higher Ron pulls the drain lower, which stabilizes the drain to remain below ground during the secondary cycle. 1-2% out  of 100 pulses were missed w. 20mOhm = Ron. No misses w. 24mOhm = Ron. Rdrain was lowered to 2.05K. This appears to be working. We may raise this to 2.2K or so after bench testing. 

All that said, we find the higher Ron, the more stable the comparator etc. However, for every 10mOhm added, we are adding 500mW in loss. (that is assuming the MOSFET runs at the equivalent load of 7Arms out - 168W). Once Infineon delivers the samples we will be rerunning the data expeditiously. I had published preliminary data on the LT8316 page. My calculations show that the LT8309 will improve overall efficiency to 93%. stay tuned. comments welcome.

see healthy cycle and premature cycle.

for those interested in deeping into SR issues...(using the LT8316 and LT8309 in a 150W nominal - 180W peak design )

Just received the MOSFETs form INFINEON.

As shown in the simulation models above (SPICE L0 for the 13mOhm and 20mOhm MOSFETs) the new MOSFETs address the issue. In essence, I have confirmed experientially the Q2drain is now pulled far enough below ground to stabilize the SR system. (see waveforms)

The system produces (as has been modeled) 24V out at a peak efficiency of 93.1% at a nominal power of 150W. The efficiency at 170W output is still 92%. The converter has been under extended stress tests at 170W output with no issues. (all thermal imaging shows <70C for all components)

Also note: add ons:

1. The SR stage in its final form has a 150V zener across the MOSFET to clamp the voltage and protect the drain pin on the LT8309. 

2. We will be adding 4.7pF to the built in 15pF capacitance of the drain pin to further lengthen the on delay and to filter additional unwanted ringing. this improves sub 50W performance  when using 13mOhm and 20mOhm MOSFETs. 

3. the drain pin will be protected by a 130V zener to further reduce the risk of damage to the pin.

We will issue a detailed 0-180W performance report once complete.

Thank you for reading 

Kindest regards 

See below: waveform shows this QR BCM converter (w 13mOhm secondary MOSFETs ) producing

170W continuous @ 24V with no issues. (yellow is Q2 drain and purple is Q2 gate)  scope is 200MHz in 14 bit mode

130W continuous with no issues. (yellow is Q2 drain purple is Q2 gate).

Hello all, 

Just a few charts as promised. (This is after a couple days of automated load testing, data collection etc.)

In summary, The PSS4_Rev004.43.005 is a compact isolated 375V to 24VDC 160W converter design using the LT8316 and the LT8309 and the ADuM4195. (BOM less than 30$ in volume)

I believe this data set shows that that flybacks can operate well above 100W in QR-BCM and produce 90% efficiency.

It also shows that the Quasi resonant concept combined with a self activated SR system imposes deadtime onto the overall cycle thus limits frequency and energy transfer. (It limits itself at around 170-180W). There is obviously the idea to increase Vin to 400VDC, which would lift the energy balance capability. However, it would require significant component changes etc. 

Also note: When using 50A 13mOhm MOSFETs for SR we added 15pF to the Vdrain pin on the LT8309. This enabled the converter to run in SR mode from 0-170W. We acknowledge it introduces a set of additional ON delays which adds to deadtime. We will be experimenting with 4.7pF 6.8pF and 10pF to examine the best stability.

All in all, the SR system combined with an CLC PI filter and a ADuM based feedback loop delivers excellent stability (loop gain and phase margin etc.).  Kind regards 

See graphs below: