The driver for this question is my desire to use LTC4416 to switch between a primary DC power source that occasionally goes away and a secondary DC source that is always present but has limited lifetime. According to the LTC4416 data sheet this is the use case that the product targets.
The ADI datasheet for this part contains this schematic on page 8:
It's helpful to remind the reader that the back-to-back MOSFETs (Q2 and Q3) in the lower right corner are **PMOS** FETs. LTC4416 is specifically designed for PMOS external FETs.
I never liked the way that LTC's datasheet drafting team drew their FETs in figures, so I redrafted Figure 2 in my Altium Designer to show the PMOS FETs as I was taught to draw them. My transistor symbols show the body diodes that are key to operation of a back-to-back PMOS transistor pair. And I identify the source and drain pins of these FETs.
The purpose of having these back-to-back PMOS FETs in the battery back-up path is to prevent (reverse) charging of the battery by the VSYS or VS rail.
No problem up to this point.
But my thumbnail analysis of the back-to-back PMOS transistors suggests that when this pair conducts one transistor is operating in quadrant 1 with its channel enhanced (no current in the body diode) and the other transistor operates in quadrant 3 with **all** current flowing through its body diode. 
But I thought that one of the virtues of LTC4416's design is to operate the conducting external transistors used in the steering paths as ideal diodes with their body diodes bypassed to the adjacent enhanced channels.
Am I misunderstanding the operation of back-to-back PMOS FETs and the LTC4416 does in fact create idealized diodes in the conducting paths where I believe that they are just 0.7V body diodes?
Best regards from steamy Indianapolis US.
