Re: gate drive was not enabled for driving the parallel mosfets

Hi,

from the voltages you measured, the key clue is OUT ≈ 1.1 V and GATE ≈ 1.2 V. For LTC4366 High Voltage Surge Stopper - Analog, the charge pump does not start until OUT is above the UVLO2 threshold, typically 4.75 V above VSS; before that, GATE is only charged by the weak startup current source. The datasheet states that once OUT exceeds 4.75 V, the charge pump turns on and charges GATE to about 12 V above OUT.

So the IC is likely not failing to activate the charge pump; rather, the circuit is never reaching the OUT voltage needed to enable the charge pump.

What your readings suggest

Assuming these voltages are measured with respect to circuit ground / VSS:

Most probable root cause

1. OUT pin is not being pulled up during startup

The LTC4366 High Voltage Surge Stopper - Analog startup sequence is:

1. VDD shunt regulator powers internal logic through RIN.
2. A weak internal startup current source charges GATE.
3. The external N-MOSFET begins to pass current and raises OUT.
4. When OUT crosses 4.75 V above VSS, the charge pump starts.
5. GATE then rises to around 12 V above OUT.

Your OUT = 1.1 V means step 3 is not happening properly. That usually points to one of these:

• MOSFET source/drain orientation is wrong.
• Back-to-back MOSFET connection is not compatible with the LTC4366 startup path.
• OUT pin is connected to the wrong MOSFET node.
• Load side is shorted or heavily loaded during startup.
• Gate is externally clamped or pulled down.
• OUT capacitor / VSS / BASE return is connected incorrectly.

So I would focus on startup path, MOSFET orientation, OUT/VSS/BASE connection, and gate clamp/leakage.

Recommended resolution path

1. Measure all IC pins with respect to VSS.
2. Temporarily remove load and check whether OUT rises.
3. Tie BASE to VSS if unused.
4. Check OUT capacitor return to VSS.
5. Inspect back-to-back MOSFET orientation and confirm OUT pin is on the correct source/common-source node.
6. Check external gate clamps/pull-downs; anything drawing more than a few µA can defeat startup.

Please share your schematic for review.

Regards,

Tech Support

Hi Harshal,

Thanks for your feedback.

In attached schematic, My observations (based on recommended solutions) are below: 

--> Out pin is connected to final drain output instead of Mosfet Common source node.

--> Timer, Base, VSS and Out capacitor are connected to Gnd. (should be connected to Rss first ).

Any other design modifications /corrections required to enable the gate drive??

Hi,

Are you able to get proper output now?

Regards,

Harshal

Hi Harshal,

After design Modifications, gate drive is enabled and Output crosses above 4.75V..thanks