Hello,
I have a PCB design with GND split into GNDA and GNDAclean. GNDAclean is on TOP layer L1 and inner layer L2. The design includes 4 LT3045 regulators placed at various locations on the PCB on layer L4 (bottom). Layers L3 and L4 carry all decoupling currents of the connected integrated circuits.
Originally I intended to connect the GND pins of the LT3045 regulators via dedicated traces routed on L3 from a reference starpoint directly to each GND pin. However, this now seems like an unfortunate solution because the GND pin is galvanically connected to the exposed pad, which would result in multiple VIA connections between the starpoint and the GNDA polygon on the bottom layer — which I consider problematic.
I need advice on how to resolve this situation. Two options come to mind: either keep the dedicated GND pin connections and create an isolated GND island around each exposed pad (which would certainly worsen thermal performance), or abandon the separate GND pin routing and instead use the GND from the bottom layer GNDA polygon where all decoupling currents flow.
VIN for the LT3045 is 6.5V, VOUT is 5V, and the current for the most loaded section is 150mA.
Thank you very much.
Could you please advise how to resolve this situation with respect to achieving the lowest possible power supply noise? Any suggested solution would be appreciated.
