ADP5055 Compensation components verification - How to do (LTSPICE not allowed)

update:
I tried to use SIMPLIZ/SIMETRIX simulation files from linkhttps://www.analog.com/media/en/simulation-models/simplis/adp5050_simplis_schematics.zip.
I am getting following error during simulation running.

"

*** ERRORS REPORTED BY SIMPLIS ***

On SIMetrix/SIMPLIS , Version : 9.40

****************************************

<<<<<<<< Error Message ID: 1038 >>>>>>>>

input file C:\wrk\ARIA\VREGChecks\adp5050_simplis_schematics\SIMPLIS_Data/ADP5050_1_2_3_CH1CH2_Buck.deck, line 442:

E1 12 27 11 27 {1+FswTOL/100)}

A number to represent the value

for 'proportionality constant' is expected at the

location where '{1+FswTOL/100)}' occupies.

On SIMetrix/SIMPLIS , Version : 9.40

*** END SIMPLIS ERROR REPORT ***

"

Hi,

Thanks for contacting Analog devices!

Your schematic exactly matching with ADI design calculation provided in page number 36 and 37. Compensation value won't change much with 1V and 1.2V output voltage. 

You can use same compensation value mention on page number 37. 

The Rc value is relatively high, which provides a strong phase margin. However, it may sometimes lead to a larger overshoot peak. If necessary, you can reduce Rc as mentioned in datasheet page no. 37 during hardware implementation. Regardless, the system will remain stable, so these values are acceptable.

regards,

Harshal

Hi Harshal,

Thanks for quick response,

I have also calculated the design values as per design example which is starting from pg36(For my reference/validation),

By keeping same L,Cout, Rcfg1,Rcfg2,Rramp(402k), my calculation gives Rc = ~23k (24.9k exactly), Cc=~0.925nF (1nF exactly), 

Cout's fZ,fP are 1.192Mhz,6.914Khz

Compensation N/W's fZ,fP are 6.392Khz, ~6.4Mhz(Ccp=1pF)

From this only, I got confidence to take the nearest values from the calculation to the design. Thanks for reiterating it.

But,Because of the Cout(~133uF) is much less here compared our design(~584uF); fZ(Cout),fP(Cout),Rc,Cc, fZ(Rc),fP(Rc) will vary, definitely response will very different from the datsheet pg36 design.

our design Cout(584uF) ~5x133uF, So, Rc also increased accordingly.

One difference or confusion for me is, My simulated response below, Phase graph starts from ~89.9degrees at 100hz (Because of 1/s term adding -90degrees to the reponse from zero frequency- not sure my analysis is correct or not), but Figure 56 from datasheet shows, phase starting from ~8 degrees.

As per your suggestion, from pg37, fc suggested as 60Khz, by taking it, 

My Rc=~83.9K(took 84.5k), Cc=~1.98nF(took 2.2nF), Ccp=~4pF, from these values

fZ(Cout),fP(Cout) are 499.65 Khz,952Hz,

fZ(Rc,Cc),fP(Rc,Cc) are 856Hz, 471.73Khz

Below simulated response.

Do you see any issues with above values.?

Can you also comment on the SIMPLIS model error also.

Hi,

There is no issue with your calculation. It might be because SIMPLIS uses average modeling for close loop compensation calculation.

As I mentioned in my earlier massage:"The Rc value is relatively high, which provides a strong phase margin. However, it may sometimes lead to a larger overshoot peak. If necessary, you can reduce Rc as mentioned in datasheet page no. 37 during hardware implementation. Regardless, the system will remain stable, so these values are acceptable."

Regards,

Harshal

Hi Harshal,

I am using other channels also.

Ch2:

Vin- 12V, Vout -3.3V@ 5%, Iout=0.7A, max of 1A,

Min L comes ~11uH, inductor used:XGL4040-103MEC (10uH)

Cout present C3216X5R107MDP(100uF)x2+CL10A226MP8NUNE(22uF)x2

Cout_DCbias=228uF, ESR_total=0.75mOhms.

Rfb1=45.3K, Rfb2=10K,Rramp=5MOhms

Rc calculated=~108Khz(took 110k), Cc calculated=~9.78nF(took 10nF), Ccp=~2pF

fZ_cout,fP_cout are 930.8Khz,148Hz;

fZ_comp,fP_comp are 145Hz,723.6Khz;

Below is simulated response.

Because of less current demand, the expected inductance coming large, AND I am not sure on what effect does LC N/W will have on Stability.

Do you see any issues with the values?

Ch3:

Vin- 12V, Vout -1.8V@ 2.5%, Iout=1A, max of 1.3A,

Min L comes to 5.5uH, Inductor used :XGL4030-562MEC

Cout present C3216X5R107MDP(100uF)x2+CL10A226MP8NUNE(22uF)x2+GRM188C81C106MA73(10uF)x1

Cout_DCbias=236uF, ESR_total=0.63mOhms.

Rfb1=20K, Rfb2=10K,Rramp=1.265MOhms

Rc calc is ~ 152.7K(took 150k), Cc calc = ~2.84nF(took 2.7nF), Ccp=~1pF

fZ_cout,fP_cout are 1.07 Mhz,374 Hz;

fZ_comp,fP_comp are 393 Hz,530.91 Khz;

Below is simulated response.

Do you see any issues with the values?

Hi,

Follow fig 54 for compensation of all three output rail.

Regards,

Harshal

Ok, currently i am going to use values from Figure54 Design from datasheet, But those are not matching with the actual calculations. I will verify during testing these values.

Ch2:

3.3V design, with same specifications which given earlier.

Cout=3x100uF, L=3.3uH, Rramp2=1.5M,Rc=30.1K,Cc=1.5nF, Ccp=1pF(assumed), Rfb1=20k,Rfb2=4.42K, My simulation shows fc=13.8K.

fZ(Cout) - 562584; fP(Cout) - 119
fZ(Comp) - 3525; fP(Comp) - 5291065

Ch3:

1.8V with same specifications which given earlier.

Cout=2x100uF+2x22uF (Don't have 47uF in our design, need to add new entry if required), L=2.2uH, Rramp2=499k,Rc=30.9k,Cc=470p,Ccp=1pF(assumed), Rfb1=20k,Rfb2=10k. Simulation shows fc=15.41K

fZ(Cout) - 930812;  fP(Cout) - 388
fZ(Comp) - 10959; fP(Comp) - 5161604